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    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    2.
    发明公开
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    方法形成自对准DOPPELSALIZID CMOS技术

    公开(公告)号：EP1825508A4

    公开(公告)日：2009-06-24

    申请号：EP05852638

    申请日：2005-12-01

    Applicant: IBM

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    Selective nitriding of gate oxide film
    4.
    发明专利
    Selective nitriding of gate oxide film 有权
    栅极氧化膜的选择性硝化

    公开(公告)号：JP2005210123A

    公开(公告)日：2005-08-04

    申请号：JP2005011499

    申请日：2005-01-19

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BURNHAM JAY S ,  ELLIS-MONAGHAN JOHN J ,  NAKOS JAMES S ,  QUINLIVAN JAMES J

    IPC: H01L27/092 ,  H01L21/318 ,  H01L21/8238 ,  H01L29/78

    CPC classification number: H01L21/823857

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including a thin gate dielectric in which nitrogen is selectively enriched.
    SOLUTION: Although an introducing amount of nitrogen is sufficient to cause gate leakage and the infiltration of a dopant to be reduced, or to prevent these, the amount does not decrease device performance much. Nitrogen lower than that of a gate dielectric of nFET in density is introduced into a gate dielectric of a pFET. Nitriding can be selectively carried out by rapid thermal nitridation (RTN), furnace nitriding, remote plasma nitriding (RPN), decoupled plasma nitriding (DPN), and wale implantation or polysilicon implantation, or by various techniques, including combinations of these methods.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 解决的问题：提供一种包括选择性富集氮气的薄栅电介质的半导体结构。 解决方案：尽管氮的引入量足以导致栅极泄漏和掺杂剂的渗透减少，或者为了防止这些，但是量不会大大降低器件性能。 低于nFET的栅极电介质的密度的氮被引入pFET的栅极电介质中。 氮化可以通过快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），纵行注入或多晶硅注入，或通过各种技术（包括这些方法的组合）来选择性地进行。 版权所有（C）2005，JPO＆NCIPI

    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    6.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    在CMOS技术中形成自对准双重杀菌剂的方法

    公开(公告)号：WO2006060575A2

    公开(公告)日：2006-06-08

    申请号：PCT/US2005043474

    申请日：2005-12-01

    Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

    OXIDE BASED LED BEOL INTEGRATION
    7.
    发明申请
    OXIDE BASED LED BEOL INTEGRATION 审中-公开
    基于氧化物的LED光束整合

    公开(公告)号：WO2012082478A3

    公开(公告)日：2012-08-02

    申请号：PCT/US2011063640

    申请日：2011-12-07

    Applicant: IBM ,  NAKOS JAMES S

    Inventor： NAKOS JAMES S

    IPC: H01L33/36 ,  H01L33/00 ,  H01L33/22

    CPC classification number: H01L33/38 ,  H01L33/0033 ,  H01L33/08 ,  H01L33/20 ,  H01L33/24 ,  H01L2933/0016 ,  H05B33/26

    Abstract: A light emitting diode (LED) structure (Fig 6g) and method for making a light emitting diode are disclosed. The structure comprises deep trench metal electrodes (385) between which electroluminescent material (320) is disposed on the sidewalls of the electrodes, (385) forming a series of luminescent diode elements stacked horizontally on a substrate. (See Fig 6g). The method for fabricating the light emitting diode structure can be used for a wide variety of electroluminescent materials.

    Abstract translation: 公开了一种发光二极管（LED）结构（图6g）和制造发光二极管的方法。 该结构包括深沟槽金属电极（385），其间电致发光材料（320）设置在电极的侧壁上，（385）形成水平堆叠在衬底上的一系列发光二极管元件。 （参见图6g）。 用于制造发光二极管结构的方法可用于各种各样的电致发光材料。

    FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
    8.
    发明申请
    FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    电力电容器模块，制造方法和设计结构

    公开(公告)号：WO2011163429A3

    公开(公告)日：2012-02-23

    申请号：PCT/US2011041546

    申请日：2011-06-23

    Applicant: IBM ,  GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

    Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

    IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L28/55 ,  H01L27/11507

    Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20,44a) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (44a) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

    Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20,44a）形成到顶板（32）和底板（28）。 至少到顶板（32）的接触（44a）和与CMOS结构的扩散的接触（20）通过公共电线电连接。

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