公开(公告)号：JP2003022677A

公开(公告)日：2003-01-24

申请号：JP2002176831

申请日：2002-06-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： WONG ROBERT C

IPC: G11C11/413 ,  G11C11/41 ,  G11C11/412

CPC classification number: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide a method for preparing a memory cell of computer for data writing operation. SOLUTION: The memory cell 202 has a cell voltage source whose one end is connected to a pull-up device in a memory cell and whose another end is connected to a pull-down device in the memory. The memory cell has, further, a pair of access transistor coupling the memory cell selectively to a pair of complementary bit line. In one embodiment, this method comprises a step in which voltage of a cell voltage source is adjusted to a second voltage value from a first voltage value. In this case, the second voltage value is lower than the first voltage value. Next, data write-in operation is made easy by coupling the memory cell to a pair of complementary bit lines BL, BR. Succeeding to write-in operation, voltage of a cell voltage source is returned to the first voltage value from the second voltage value.

Abstract translation: 要解决的问题：提供一种用于准备用于数据写入操作的计算机的存储单元的方法。 解决方案：存储单元202具有单元电压源，其一端连接到存储单元中的上拉器件，并且其另一端连接到存储器中的下拉器件。 此外，存储器单元还具有将存储器单元选择性地耦合到一对互补位线的一对存取晶体管。 在一个实施例中，该方法包括其中电池电压源的电压从第一电压值调节到第二电压值的步骤。 在这种情况下，第二电压值低于第一电压值。 接下来，通过将存储器单元耦合到一对互补位线BL，BR来使数据写入操作变得容易。 继续写入操作，单元电压源的电压从第二电压值返回到第一电压值。

公开(公告)号：JPS62102557A

公开(公告)日：1987-05-13

申请号：JP21422086

申请日：1986-09-12

Applicant: IBM

Inventor： WONG ROBERT C

IPC: H01L27/088 ,  G11C11/41 ,  G11C11/411 ,  H01L21/8226 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102

公开(公告)号：WO2007084848A3

公开(公告)日：2007-12-06

申请号：PCT/US2007060474

申请日：2007-01-12

Applicant: IBM ,  CHAN JOSEPH Y ,  WONG ROBERT C

Inventor： CHAN JOSEPH Y ,  WONG ROBERT C

IPC: H01L29/94 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L29/7843

Abstract: A single stress liner (120) is applied over different type semiconductor devices. The single stress liner (120) avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner (120) may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs (110) and PFETs (112).

Abstract translation: 单个应力衬垫（120）被施加在不同类型的半导体器件上。 单应力衬垫（120）通过消除会议面积避免双重/混合应力衬垫方案的问题。 单个应力衬垫（120）可以是拉伸或压缩的。 在一个实施例中，半导体器件包括具有许多NFET（110）和PFET（112）的静态随机存取存储器（SRAM）单元。

公开(公告)号：JP2007149325A

公开(公告)日：2007-06-14

申请号：JP2006317757

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ELLIS WAYNE F ,  MANN RANDY W ,  WAGER DAVID J ,  WONG ROBERT C

IPC: G11C11/413 ,  G11C11/412

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: PROBLEM TO BE SOLVED: To provide a static/random/access/memory (SRAM) including a plurality of SRAM cells arranged in an array state.
SOLUTION: The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control circuit corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuit is coupled to an output of a power supply. Each voltage control circuit has a function to temporarily reduce voltage provided to the power supply input of a plurality of SRAM cells that belong to the selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括以阵列状态排列的多个SRAM单元的静态/随机/存取/存储器（SRAM）。 解决方案：阵列包括多个行和多个列。 SRAM包括与阵列的多个列中的相应列对应的多个电压控制电路。 多个电压控制电路中的每一个耦合到电源的输出端。 每个电压控制电路具有临时降低提供给属于SRAM的选定列列的多个SRAM单元的电源输入的电压的功能。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005236282A

公开(公告)日：2005-09-02

申请号：JP2005026929

申请日：2005-02-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN PHUNG T ,  WONG ROBERT C

IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC classification number: G11C11/412 ,  H01L27/1104 ,  Y10S257/903

Abstract: PROBLEM TO BE SOLVED: To provide contacts of P well and N well and, suitably, a low cost SRAM (static random access memory) cell having a P+ a diffusion intersection section to ground.
SOLUTION: The SRAM cell is completed at second metal (M2) level, and the leakage, function and manufacturing yield in cell path gate are improved. The SRAM cell is provided with cross-linked pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, the P1, P2 devices are connected to a power supply VDD, and the N1 N2 devices are connected to the ground through the P + diffusion area. A first gate is connected between the junction of a first bit line and the device P1, and N1, and the gate is connected to a word line. And a second path gate is connected between the junction of a second bit line and the device P2 and N2, and the gate is connected to the word line.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供P阱和N阱的接触，以及适当地，具有到接地的P + a扩散交叉部分的低成本SRAM（静态随机存取存储器）单元。 解决方案：SRAM单元在第二金属（M2）级完成，提高了单元路径栅极的泄漏，功能和制造产量。 SRAM单元提供有交叉连接的pnp上拉器件P1，P2和npn下拉器件N1，N2，P1，P2器件连接到电源VDD，N1 N2器件连接到地 通过P +扩散区域。 第一栅极连接在第一位线与器件P1的结和N1之间，栅极连接到字线。 并且第二路径栅极连接在第二位线的连接点和器件P2和N2之间，并且栅极连接到字线。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AU2002306174A1

公开(公告)日：2003-12-31

申请号：AU2002306174

申请日：2002-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J ,  WONG ROBERT C

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L23/535 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.