公开(公告)号：EP1920493A4

公开(公告)日：2011-05-04

申请号：EP06802645

申请日：2006-08-30

Applicant: IBM

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01H50/00 ,  H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

公开(公告)号：EP1836726A4

公开(公告)日：2010-07-28

申请号：EP05852629

申请日：2005-12-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL J ,  STANDAERT THEODORUS E ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1812966A4

公开(公告)日：2010-07-14

申请号：EP05848854

申请日：2005-11-09

Applicant: IBM

Inventor： CHENG KANGGUO ,  RADENS CARL J

IPC: H01L21/8242

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：EP1977425A4

公开(公告)日：2009-04-29

申请号：EP07710032

申请日：2007-01-10

Applicant: IBM

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

公开(公告)号：JP2004088100A

公开(公告)日：2004-03-18

申请号：JP2003287161

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHAN BABAR A ,  RADENS CARL J ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a built-in DRAM with a vertical device array and a bordered bit line contact, and a manufacturing method of the built-in DRAM.
SOLUTION: In an integrated circuit including a dynamic random access memory (DRAM), a DRAM cell has a storage capacitor in a deep trench, a transistor which has channels extending along side walls of the deep trench and a gate conductor in the deep trench, and a word line which makes contact with the gate conductor from above. The word line has a center line deviating from the center line of the gate conductor. The DRAM cell also has active regions extending from channels of the transistor and a bit line contact to the active regions, which are bordered by insulation spacers on side walls of the word line.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001077321A

公开(公告)日：2001-03-23

申请号：JP2000220495

申请日：2000-07-21

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY PETER ,  RADENS CARL J

IPC: B24B37/04 ,  H01L21/027 ,  H01L21/28 ,  H01L21/304 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To realize a process for manufacturing two kinds of different gate dielectric thicknesses by using a polysilicon mask and chemical mechanical polishing(CMP). SOLUTION: A thick gate dielectric 102 is grown on a substrate having a memory array area 201 and a logical device area 101, and a gate stack containing a first polysilicon layer 103 is formed on the dielectric 102. Then a thin gate dielectric 200 is formed on the substrate above the logical device area 101, and a second polysilicon layer 300 is formed in the logical device area 101. The thickness of the second polysilicon layer 300 is at least made to be equal to that of the gate stack in the memory array area 201. The structure is flattened by using chemical mechanical polishing(CMP), and the gate stack in the memory array area 201 and logical device area 101 is patterned.

公开(公告)号：JP2000138354A

公开(公告)日：2000-05-16

申请号：JP29115799

申请日：1999-10-13

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure, where depletion of majority carrier controlled by the field effect of an embedded strap region that controls access to a trench cell capacitor is used. SOLUTION: A memory cell structure is equipped with a field effect switch provided with a gate terminal 1000 possessed of a trench upper part and a depletion region in a substrate. The range of the depletion region is varied as function of a voltage applied to the gate terminal. Furthermore, a memory device having an isolation collar 400 and a capacitor is provided, and when a field effect switch is at an off-state, a depletion region is superposed on the isolation collar 400, and the depletion region will not be superposed on the isolation collar, when the field effect switch is at an on-state.

公开(公告)号：WO2007027813A3

公开(公告)日：2007-12-06

申请号：PCT/US2006033924

申请日：2006-08-30

Applicant: IBM ,  HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

Abstract: A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

Abstract translation: 描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。 开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200） 微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。