公开(公告)号：WO2004051763A3

公开(公告)日：2004-09-30

申请号：PCT/DE0303935

申请日：2003-11-27

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  KREUPL FRANZ

Inventor： HOFMANN FRANZ ,  KREUPL FRANZ

IPC: G11C13/02 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00 ,  G11C11/34

CPC classification number: G11C13/0011 ,  B82Y10/00 ,  B82Y30/00 ,  G11C2213/15 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16

Abstract: The invention relates to a method for the production of a memory cell, a memory cell and a memory cell arrangement. According to the inventive method for the production of a memory cell, a first electrically conductive area (311) is formed in and/or on a substrate (301). A second electrically conductive area (312) is also formed at a given distance from the first electrically conductive area such that a cavity (321) is formed between the first and second electrically conductive areas. The first and second electrically conductive areas are configured in such a way that when a first voltage is applied to the electrically conductive areas, a structure is formed from material from at least one of said electrically conductive areas, at least partially bridging over the distance between the electrically conductive areas. When a second voltage is applied to the conductive areas, the material of the structure at least partially bridging over the distance between the electrically conductive areas recedes.

Abstract translation: 本发明涉及一种用于制造存储器单元，存储器单元和存储器单元阵列的方法。 在用于在和/或衬底（301）上制造存储单元的方法中，第一导电区域（311）形成。 此外，在从所述第一导电区域预定距离的第二导电区域（313）被形成为使得一个腔体（321）在所述第一和第二导电区域之间形成。 第一和第二导电区域被设​​置为使得，施加第一电压时，所述导电区域中的至少一个，所述导电区域之间的距离的材料的导电区域，至少部分地桥接结构。 当将第二电压施加到材料的导电区域，导电区域至少部分地桥接结构之间的距离为倒退。

公开(公告)号：WO2006039907A2

公开(公告)日：2006-04-20

申请号：PCT/DE2005001816

申请日：2005-10-11

Applicant: INFINEON TECHNOLOGIES AG ,  DUESBERG GEORG ,  KREUPL FRANZ ,  SEIDEL ROBERT ,  STEINLESBERGER GERNOT

Inventor： DUESBERG GEORG ,  KREUPL FRANZ ,  SEIDEL ROBERT ,  STEINLESBERGER GERNOT

IPC: H01L51/40

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L51/0021

Abstract: The invention relates to an electrical circuit with at least one nanostructure and a carbon conductor track, said carbon conductor track being embodied by a layer essentially made from carbon, whereby the nanostructure and the carbon conductor track are in direct contact.

Abstract translation: 一种电路包括：至少一个纳米结构，和碳导体，它是由基本上由碳 - 碳层导体轨道的一个组，其中所述纳米结构和碳导体轨道直接接触的方式形成。

公开(公告)号：WO2005060000A3

公开(公告)日：2005-10-27

申请号：PCT/DE2004002739

申请日：2004-12-14

Applicant: INFINEON TECHNOLOGIES AG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  SPECHT MICHAEL ,  STEINLESBERGER GERNOT

Inventor： KRETZ JOHANNES ,  KREUPL FRANZ ,  SPECHT MICHAEL ,  STEINLESBERGER GERNOT

IPC: H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/792

CPC classification number: H01L29/7923 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785

Abstract: The invention relates to a bridge field-effect transistor storage cell comprising a first and second source/ drain areas and a channel area arranged therebetween which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer which is disposed at least partially on the semiconductor bridge and a metal conductive gate area on at least one part of said charge-coupled layer which is arranged in such a way that electric charge carriers are selectively introducible or removable by applying a predetermined electric voltage to the bridge field-effect transistor storage cell.

Abstract translation: 鳍式场效应晶体管存储器单元包括第一和第二源/漏区和沟道区设置在其间，在半导体桥，其形成源极/漏极和沟道区。 该存储单元还包括在至少一个被布置成使得所述电荷存储层的部分，其至少部分地布置在所述半导体桥的电荷存储层，以及金属栅极导电区域中的预先确定的通过施加电势到鳍式场效应晶体管存储器单元的装置 被选择性地引入或在电荷存储层的电荷载流子除去。

公开(公告)号：WO0115219A3

公开(公告)日：2001-07-19

申请号：PCT/DE0002811

申请日：2000-08-18

Applicant: INFINEON TECHNOLOGIES AG ,  SCHWARZL SIEGFRIED ,  ENGELHARDT MANFRED ,  KREUPL FRANZ

Inventor： SCHWARZL SIEGFRIED ,  ENGELHARDT MANFRED ,  KREUPL FRANZ

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76807 ,  H01L21/31144 ,  H01L21/76813

Abstract: The invention relates to the production of a metalicized surface having conductors and contacts wherein dielectric layers are applied to a substrate (4). Contact holes are etched through the two upper-most dielectric layers extending as far as the dielectric layers which lie below. The remaining layer thickness is approximately the same as the thickness of the upper-most layer. Thereafter, trenches for the conductors are selectively etched into the first dielectric layer and the third dielectric layer whose surface is practically laid bare at the same time. After structuring of the first dielectric layer and the third dielectric layer has taken place, contacts and conductors are arranged in the contact holes and conductor trenches.

Abstract translation: 以产生具有电介质层施加到基底上（4）引线和接触金属化。 有首先通过下面的介电层在顶部两个电介质层，其中，该层的剩余厚度基本上等于最上面Schicknt的厚度的接触孔。 随后，Leitungsgrabenätzung选择性到所述第一介电层和第三介电层，其表面的基本上同时暴露发生。 第一介电层的结构和第三介电层之后的接触和线接触孔和沟槽中产生。

公开(公告)号：WO2004040668A3

公开(公告)日：2004-07-08

申请号：PCT/DE0303612

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.

Abstract translation: 本发明涉及一种场效应晶体管装置和一种电路阵列。 场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。 此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。 纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

公开(公告)号：WO03050868A3

公开(公告)日：2003-09-04

申请号：PCT/DE0203998

申请日：2002-10-23

Applicant: INFINEON TECHNOLOGIES AG ,  KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

Inventor： KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

IPC: H01L21/768 ,  H01L51/30 ,  C01B31/02 ,  H01L23/522

CPC classification number: H01L21/7682 ,  B82Y10/00 ,  H01L51/0048 ,  H01L2221/1047 ,  Y10S977/742

Abstract: The invention relates to a method for producing a layered assembly and to a layered assembly (200). According to said method, two substantially parallel electrically conductive strip conductors (202, 203) are configured on a substrate and at least one auxiliary structure (205a, 205b, 205c) is configured on said substrate (201) between the two strip conductors (202, 203), running in a first direction (206), said first direction (206) forming an acute angle of at least 45 DEG or a right angle with a connecting axis of the strip conductors that runs at right angles to both strip conductors (202, 203). The invention is characterised in that the auxiliary structure or structures (205a, 205b, 205c) is or are produced from one material and said structure or structures can be selectively removed from the dielectric layer (204). In addition, a dielectric layer (204) is configured between the two strip conductors in such a way that the auxiliary structure or structures (205a, 205b, 205c) is or are at least partially covered by the dielectric layer (204).

Abstract translation: 本发明涉及一种用于制造层结构的方法，和层布置。 在用于制造层结构（200），两个基本上相互平行的导电迹线（202,203）的方法形成在衬底上的衬底，至少一个辅助结构（205A，205B，205C）上（201） 且沿第一方向延伸的两个导体（202，203）之间（206）形成，该第一方向（206）与垂直于延伸的互连的连接轴线的锐角或直角两个互连（202，203）至少 包括45°的角度，其中，所述至少一个辅助结构（205A，205B，205C）由介电层（204）的至少一个辅助结构是可选择性去除的材料制成。 此外，在两个导体轨道之间形成的介电层（204），使得从电介质层（204）的所述至少一个辅助结构（205A，205B，205C）至少部分地被覆盖。

公开(公告)号：WO2005033358A3

公开(公告)日：2005-07-21

申请号：PCT/EP2004010892

申请日：2004-09-29

Applicant: INFINEON TECHNOLOGIES AG ,  GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

Inventor： GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

IPC: C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/44 ,  C23C16/455 ,  H01L21/3205

CPC classification number: C23C16/0209 ,  C23C16/045 ,  C23C16/26 ,  C23C16/45557

Abstract: The invention relates to a method for depositing a carbon material (17) in or on a substrate (14). Said method comprises the following steps: the inside (10') of a processing chamber (10) is heated to a pre-determined temperature; the substrate (14) is introduced into the processing chamber (10); the air in the processing chamber (10) is evacuated until a pre-determined pressure or a lower pressure is reached; a gas (12) containing at least carbon is introduced until a second pre-determined pressure is reached, that is higher than the first pre-determined pressure; and the carbon material (17) is deposited on a surface or in a recess (15), from the gas (12) containing carbon. The invention also relates to a semiconductor contact device.

Abstract translation: 本发明提供了用于在或基板（14）上沉积的碳材料（17），其包括以下步骤的方法：处理室（10）加热的内部空间（10“）到预定的温度; 放置在处理室中的基板（14）（10）; 抽空所述处理室（10）到第一预定压力或更低; 引入气体（12），其具有至少碳，​​直到达到第二预定压力，其比第一预定压力更高; 和沉积所述碳材料（17）上的表面上或在从含碳气体（12）的凹部（15）。 本发明还提供了一种半导体接触装置。

公开(公告)号：WO2004040644A3

公开(公告)日：2004-08-12

申请号：PCT/DE0303589

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8239 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/16 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L51/057

Abstract: The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

Abstract translation: 本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。 该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

公开(公告)号：WO02099845A3

公开(公告)日：2003-08-21

申请号：PCT/DE0202026

申请日：2002-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  KREUPL FRANZ ,  SIMBUERGER WERNER

Inventor： HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  KREUPL FRANZ ,  SIMBUERGER WERNER

IPC: H01L25/18 ,  H01L21/60 ,  H01L23/485 ,  H01L25/065 ,  H01L25/07 ,  H01L23/498 ,  C01B31/02 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  B82Y30/00 ,  G01R31/2884 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13193 ,  H01L2224/16145 ,  H01L2224/81065 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A plurality of nanotubes is mounted on at least one external metallic chip contact of the electronic chip for contacting said electronic chip with an additional electronic chip.

Abstract translation: 在电子芯片中的至少一个外部片金属接触多个纳米管被应用于电子芯片与另外的电子芯片接触。

公开(公告)号：WO03061004A2

公开(公告)日：2003-07-24

申请号：PCT/DE0300080

申请日：2003-01-13

Applicant: INFINEON TECHNOLOGIES AG ,  BREDERLOW RALF ,  ELBE ASTRID ,  KREUPL FRANZ ,  LUYKEN JOHANNES ,  NEUHAUSER ROBERT ,  PAULUS CHRISTIAN ,  SCHEPERS JOERG ,  THEWES ROLAND

Inventor： BREDERLOW RALF ,  ELBE ASTRID ,  KREUPL FRANZ ,  LUYKEN JOHANNES ,  NEUHAUSER ROBERT ,  PAULUS CHRISTIAN ,  SCHEPERS JOERG ,  THEWES ROLAND

IPC: G06K19/073 ,  H01L23/58 ,  H01L23/544

CPC classification number: B82Y10/00 ,  G06K19/073 ,  G06K19/07372 ,  H01L23/576 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: According to the invention, an electrical characteristic of a material layer (3) or layer-type material structure is measured at various points provided with connection contacts (5, 6). A mean value of the measurement, taken from a base set of IC chips, is subtracted from a respective value, and a digital word for identifying the chip in question is formed on the basis of the result thus obtained, for each IC chip. The measurement can be carried out by means of a cross-correlation, the measuring regions crossing over each other.

Abstract translation: 一材料层（3）或所述材料的层状结构的电特性在不同的位置进行测定，与所述连接接点（5,6）被提供。 采取大约IC芯片平均测量的群的部分中的相应值的是由和由这样获得的结果，以每个IC芯片，一个数字字为各个芯片的识别中减去。 所述测量可以用互相关，其中，所述测量范围被交叉地设置制成。