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公开(公告)号:WO0214886A3
公开(公告)日:2002-07-11
申请号:PCT/US0123168
申请日:2001-07-23
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: LEHMANN GUNTHER , FRANKOWSKY GERD , HSU LOUIS , REITH ARMIN
IPC: G01R31/3183 , G01R31/319 , G11C29/10 , G11C29/56 , G11C29/00
CPC classification number: G11C29/10 , G01R31/3183 , G01R31/31926 , G11C29/56
Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.
Abstract translation: 用于在存储器电路中生成逻辑硬件测试模式的自动方法基于给定的物理模式。 该方法包括从给定的一组逻辑数据模式向后转换。 由于该方法是自动的,因此不需要知道存储器电路内的数据加扰。
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公开(公告)号:WO0229825A3
公开(公告)日:2002-08-01
申请号:PCT/US0127001
申请日:2001-08-30
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: LEHMANN GUNTHER , FRANKOWSKY GERD , HSU LOUIS L , REITH ARMIN
IPC: G01R31/3183 , G01R31/319 , G11C29/10 , G11C29/56 , G11C29/00
CPC classification number: G01R31/318378 , G01R31/3183 , G01R31/31926 , G11C29/10 , G11C29/56
Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.
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公开(公告)号:WO0229894A2
公开(公告)日:2002-04-11
申请号:PCT/US0127143
申请日:2001-08-30
Applicant: INFINEON TECHNOLOGIES CORP
Inventor: REITH ARMIN , LEIDINGER TINA , LEHMANN GUNTHER
IPC: G11C7/06 , H01L27/108 , G11C11/4091
CPC classification number: G11C7/065 , H01L27/10897
Abstract: A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.
Abstract translation: 在硅集成电路中形成用于动态随机存取存储器的读出放大器。 这种读出放大器的阵列的间距等于存储器阵列的位线对的间距。 每个读出放大器阵列由具有U形栅电极的给定n或p沟道型金属氧化物半导体(MOS)晶体管的四行晶体管形成。 读出放大器的每行晶体管中的晶体管的栅电极以预先选定的量偏离前一行。 通过读出放大器的位线是直的,没有偏移影响光刻性能,也没有突起增加位线的电容。 这种读出放大器阵列的尺寸等于位线对的最小尺寸,因此不会导致存储器单元阵列的宽度的任何增加。
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公开(公告)号:DE60104015T2
公开(公告)日:2005-06-30
申请号:DE60104015
申请日:2001-08-30
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: LEHMANN GUNTHER , FRANKOWSKY GERD , HSU LOUIS L , REITH ARMIN
IPC: G01R31/3183 , G01R31/319 , G11C29/10 , G11C29/56 , G11C29/00
Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.
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公开(公告)号:DE60104015D1
公开(公告)日:2004-07-29
申请号:DE60104015
申请日:2001-08-30
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: LEHMANN GUNTHER , FRANKOWSKY GERD , HSU LOUIS L , REITH ARMIN
IPC: G01R31/3183 , G01R31/319 , G11C29/10 , G11C29/56 , G11C29/00
Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.
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