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    AREA EFFICIENT STACKING OF ANTIFUSES IN SEMICONDUCTOR DEVICE
    1.
    发明申请
    AREA EFFICIENT STACKING OF ANTIFUSES IN SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件中有效地堆叠抗体

    公开(公告)号：WO02061826A3

    公开(公告)日：2003-01-16

    申请号：PCT/US0148819

    申请日：2001-12-17

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： LEHMANN GUNTHER ,  BRINTZENGER AXEL ,  DANIEL GABRIEL

    IPC: H01L23/525

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is provided which is formed of a wafer (101) having on a surface thereof an area efficient arrangement of at least two antifuses (121, 122) in vertically stacked relation and sharing a common intermediate electrode (123) therebetween. The arrangement includes at least one lower antifuse (121) having a lower counter electrode (125) and a lower fusible insulator portion (124) defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode (125) with the common intermediate electrode (123), and at least one upper antifuse (122), the upper antifuse (122) having an upper counter electrode (127) and an upper fusible insulator portion (126) defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode (127) with the common intermediate electrode (123).

    Abstract translation: 提供一种半导体器件，其由晶片（101）形成，晶片（101）在其表面上具有垂直堆叠关系的至少两个反熔丝（121,122）的区域有效布置，并且在其间共享公共中间电极（123）。 该装置包括至少一个具有下部对电极（125）和下部可熔绝缘体部分（124）的下部反熔丝（121），该下部可熔绝缘体部分（124）限定了初始高电阻状态的下部熔断元件，其将下部对置电极（125）与 公共中间电极（123）和至少一个上部反熔丝（122），上部反熔丝（122）具有上部对电极（127）和上部可熔绝缘体部分（126），其限定了初始高度的上部熔丝元件 将上部对置电极（127）与公共中间电极（123）相互连接的电阻状态。

    OPTIMIZED DECOUPLING CAPACITOR USING LITHOGRAPHIC DUMMY FILLER
    2.
    发明申请
    OPTIMIZED DECOUPLING CAPACITOR USING LITHOGRAPHIC DUMMY FILLER 审中-公开
    优化的解压电容器使用LITHOGRAPHIC DUMMY FILLER

    公开(公告)号：WO0137320A3

    公开(公告)日：2001-12-06

    申请号：PCT/US0030404

    申请日：2000-11-02

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： REITH ARMIN M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

    IPC: G06F17/50 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    CPC classification number: H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

    Abstract translation: 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

    SENSE AMPLIFIER
    5.
    发明申请
    SENSE AMPLIFIER 审中-公开
    感应放大器

    公开(公告)号：WO0229894A2

    公开(公告)日：2002-04-11

    申请号：PCT/US0127143

    申请日：2001-08-30

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： REITH ARMIN ,  LEIDINGER TINA ,  LEHMANN GUNTHER

    IPC: G11C7/06 ,  H01L27/108 ,  G11C11/4091

    CPC classification number: G11C7/065 ,  H01L27/10897

    Abstract: A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.

    Abstract translation: 在硅集成电路中形成用于动态随机存取存储器的读出放大器。 这种读出放大器的阵列的间距等于存储器阵列的位线对的间距。 每个读出放大器阵列由具有U形栅电极的给定n或p沟道型金属氧化物半导体（MOS）晶体管的四行晶体管形成。 读出放大器的每行晶体管中的晶体管的栅电极以预先选定的量偏离前一行。 通过读出放大器的位线是直的，没有偏移影响光刻性能，也没有突起增加位线的电容。 这种读出放大器阵列的尺寸等于位线对的最小尺寸，因此不会导致存储器单元阵列的宽度的任何增加。

    WIRING THROUGH TERMINAL VIA FUSE WINDOW
    6.
    发明申请
    WIRING THROUGH TERMINAL VIA FUSE WINDOW 审中-公开
    通过FUSE WINDOW通过终端接线

    公开(公告)号：WO0215269A3

    公开(公告)日：2002-05-10

    申请号：PCT/US0123171

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： LEHMANN GUNTHER ,  BRINTZINGER AXEL

    IPC: H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses (106) disposed on a same level in a fuse bank (104). A plurality of conductive lines (408) are routed through the fuse bank in between the fuses. A terminal via window (405) is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

    Abstract translation: 根据本发明的半导体器件包括设置在保险丝组（104）中的同一电平上的多个保险丝（106）。 多个导线（408）在保险丝之间穿过保险丝库。 端子通孔（405）形成在多个导线上的钝化层中并在多个保险丝上形成，端子通孔被形成为暴露保险丝组中的保险丝。

    AREA EFFICIENT METHOD FOR PROGRAMMING ELECTRICAL FUSES
    7.
    发明申请
    AREA EFFICIENT METHOD FOR PROGRAMMING ELECTRICAL FUSES 审中-公开
    用于编程电熔丝的区域有效方法

    公开(公告)号：WO0233707A2

    公开(公告)日：2002-04-25

    申请号：PCT/US0145044

    申请日：2001-10-19

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： LEHMANN GUNTHER ,  DANIEL GABRIEL ,  FRANKOWSKY GERD

    IPC: G11C17/16 ,  G11C17/18 ,  G11C17/00

    CPC classification number: G11C17/18 ,  G11C17/16

    Abstract: A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register (12) including a plurality of latches (16). Each latch has a corresponding switch (22) and a corresponding electrical fuse (24). A bit generator (208) generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal (206). Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line (28) connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data (202) such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

    Abstract translation: 根据本发明的用于编程电熔丝的电路包括包括多个闩锁（16）的移位寄存器（12）。 每个闩锁具有对应的开关（22）和相应的电熔丝（24）。 位产生器（208）产生第一状态的单个位和第二状态的所有其他位。 位产生器根据时钟信号将生成的比特传播到移位寄存器（206）。 每个开关根据存储在相应的锁存器中的产生的位使能通过相应的电熔丝的导通。 吹电压线（28）连接到电保险丝。 根据编程数据（202）激活吹扫电压线以熔断熔丝，使得当第一状态的单个位被存储在对应于要编程的熔丝的锁存器中时，电熔丝根据编程数据被编程 。

    8.
    发明专利
    未知

    公开(公告)号：DE60030467D1

    公开(公告)日：2006-10-12

    申请号：DE60030467

    申请日：2000-11-02

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： REITH M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

    IPC: G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

    9.
    发明专利
    未知

    公开(公告)号：DE60030467T2

    公开(公告)日：2007-05-03

    申请号：DE60030467

    申请日：2000-11-02

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： REITH M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

    IPC: G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

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