公开(公告)号：US20240176167A1

公开(公告)日：2024-05-30

申请号：US18071246

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Tolga ACIKALIN ,  Harel FRISH ,  Sandeep GAAN ,  John HECK ,  Eric J. M. MORET ,  Suddhasattwa NAD ,  Haisheng RONG

IPC: G02F1/01 ,  G02B6/125

CPC classification number: G02F1/0113 ,  G02B6/125 ,  G02F1/0147 ,  G02B2006/12145

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

公开(公告)号：US20240071883A1

公开(公告)日：2024-02-29

申请号：US17893893

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230420348A1

公开(公告)日：2023-12-28

申请号：US17852039

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49894 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.

公开(公告)号：US20200312698A1

公开(公告)日：2020-10-01

申请号：US16363426

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI

IPC: H01L21/683 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a monolayer having a plurality of first molecules over the first surface of the package substrate. In an embodiment, the first molecules each comprise a first functional group attached to the first surface, and a first release moiety attached to the first functional group.

公开(公告)号：US20240213111A1

公开(公告)日：2024-06-27

申请号：US18088360

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Je-Young CHANG ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Brandon C. MARIN ,  Suddhasattwa NAD

IPC: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/49816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. In an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. In an embodiment, the lid seals the channel between a first end and a second end of the channel.

公开(公告)号：US20240111092A1

公开(公告)日：2024-04-04

申请号：US17956757

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

公开(公告)号：US20240111089A1

公开(公告)日：2024-04-04

申请号：US17956750

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Suddhasattwa NAD ,  Robert Alan MAY

IPC: G02B6/12 ,  B82Y20/00 ,  G02B1/115 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43

CPC classification number: G02B6/12004 ,  B82Y20/00 ,  G02B1/115 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12147 ,  G02B2006/12176

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes for improving the refractive index of the coating that optically couples with an optical medium, wherein the coating includes one or more layers that include a plurality of nanorods. The plurality of nanorods within each of the one or more layers may have a similar orientation in the chemical composition. The nanorods within separate layers may have different characteristics, including different orientations, different sizes, and/or different chemical compositions. Other embodiments may be described and/or claimed.

公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20230079607A1

公开(公告)日：2023-03-16

申请号：US17473099

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L21/48 ,  H01L21/683

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.