公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20240176167A1

公开(公告)日：2024-05-30

申请号：US18071246

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Tolga ACIKALIN ,  Harel FRISH ,  Sandeep GAAN ,  John HECK ,  Eric J. M. MORET ,  Suddhasattwa NAD ,  Haisheng RONG

IPC: G02F1/01 ,  G02B6/125

CPC classification number: G02F1/0113 ,  G02B6/125 ,  G02F1/0147 ,  G02B2006/12145

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20190279806A1

公开(公告)日：2019-09-12

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Sandeep GAAN ,  Sri Ranga Sai BOYAPATI ,  Prithwish CHATTERJEE ,  Sameer PAITAL ,  Rahul JAIN ,  Junnan ZHAO

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US20200245472A1

公开(公告)日：2020-07-30

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Sandeep GAAN ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Ke LIU ,  Suddhasattwa NAD ,  Marcel A. WALL ,  Rahul N. MANEPALLI ,  Ravindra V. TANIKELLA

IPC: H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  C23C18/16 ,  C23C18/18 ,  C23C18/38

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20190206786A1

公开(公告)日：2019-07-04

申请号：US15857454

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Sandeep GAAN ,  Srinivas V. PIETAMBARAM ,  Sameer R. PAITAL

IPC: H01L23/50 ,  H01L23/498 ,  H01L49/02 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L23/49822 ,  H01L28/20 ,  H01L28/40

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.