公开(公告)号：JPH08331517A

公开(公告)日：1996-12-13

申请号：JP18698995

申请日：1995-07-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BUN YOUSEKI ,  KIN SHICHIYUU ,  CHIYOU JIYUNKA

IPC: H04N7/01 ,  H04N1/41 ,  H04N19/42 ,  H04N19/423 ,  H04N19/60 ,  H04N19/625

Abstract: PROBLEM TO BE SOLVED: To facilitate an ASIC by forming a scan system conversion circuit which is an address generator for scan system conversion, only with a pure logic circuit. SOLUTION: An up/down counting circuit part 1 up counts values from one to N-1 and then down counts to one. A down-counting circuit part 2 counts down from an output value of the 1 to zero and generates a carry signal. A 1st selecting part 3 alternately selects values of the N-1 and -(N-1) and outputs them. A 2nd selecting part 4 alternately selects values one and N and outputs them. A 3rd selecting part 5 selects final output data with the outputs of the parts 3 and 4 as inputs. A phase-converting circuit part 7 changes an output phase of the part 4 at the point of time, when the N-1 or the -(N-1) has occurred at N-1 times. An accumulating part 8 generates a final address output signal by accumulating the outputs of the part 5.

公开(公告)号：JPH09163370A

公开(公告)日：1997-06-20

申请号：JP20584896

申请日：1996-08-05

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KENSHIYU ,  KIN SHICHIYUU

IPC: H04N7/24 ,  G06T9/00 ,  H03M7/30 ,  H04N1/41 ,  H04N19/423 ,  H04N19/60 ,  H04N19/625 ,  H04N19/93 ,  H04N7/30

Abstract: PROBLEM TO BE SOLVED: To accelerate operating speed by composing a circuit only of a circuit using the regularity of scanning address patterns. SOLUTION: A sequential address generating part 21 inputs a start signal, clock signal and control signal and generates sequential addresses. A scanning address generating part 22 inputs a start signal, a clock signal and a control signal and generates a zigzag scanning address signal and an alternate scanning address signal. Based on the control signal, the 1st and the 2nd multiplexers 23 select the respective address signals from both address generating parts 21 and 22. A latch part 24 outputs the selected address signal while controlling timing.