公开(公告)号：JPH08331517A

公开(公告)日：1996-12-13

申请号：JP18698995

申请日：1995-07-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BUN YOUSEKI ,  KIN SHICHIYUU ,  CHIYOU JIYUNKA

IPC: H04N7/01 ,  H04N1/41 ,  H04N19/42 ,  H04N19/423 ,  H04N19/60 ,  H04N19/625

Abstract: PROBLEM TO BE SOLVED: To facilitate an ASIC by forming a scan system conversion circuit which is an address generator for scan system conversion, only with a pure logic circuit. SOLUTION: An up/down counting circuit part 1 up counts values from one to N-1 and then down counts to one. A down-counting circuit part 2 counts down from an output value of the 1 to zero and generates a carry signal. A 1st selecting part 3 alternately selects values of the N-1 and -(N-1) and outputs them. A 2nd selecting part 4 alternately selects values one and N and outputs them. A 3rd selecting part 5 selects final output data with the outputs of the parts 3 and 4 as inputs. A phase-converting circuit part 7 changes an output phase of the part 4 at the point of time, when the N-1 or the -(N-1) has occurred at N-1 times. An accumulating part 8 generates a final address output signal by accumulating the outputs of the part 5.

公开(公告)号：JPH09259115A

公开(公告)日：1997-10-03

申请号：JP29170596

申请日：1996-11-01

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KENSHIYU ,  CHIYOU JIYUNKA ,  KEN YOSHIHIRO

IPC: G11C7/00 ,  G06F7/78 ,  G06F17/16 ,  G11C8/00

Abstract: PROBLEM TO BE SOLVED: To convert respective inputted data into bit-serial data and speedily perform transposing operation for a matrix by storing respective registers with K/N-bit data selected by an output multiplexer module means, and then integrating N K/N-bit data into one data and outputting it as K-bit data. SOLUTION: A bit-serial transposing module means 12 selects and outputs shifted K/N-bit data, outputted by an input shift register module means 11, with a switching control signal. The output multiplexer module means 13 selects and outputs the K/N-bit data, outputted by the bit-serial transposing module means 12, by respective multiplexers. An output register module means 14 stores the respective registers with the K/N-bit data selected by the output multiplexer module means 13, and then integrates N K/N-bit data into one data, which is outputted as K-bit data.

公开(公告)号：JPH0884346A

公开(公告)日：1996-03-26

申请号：JP18085695

申请日：1995-06-23

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： CHIYOU JIYUNKA ,  BUN YOUSEKI

IPC: H04N19/182 ,  H04N1/41 ,  H04N5/14 ,  H04N7/24 ,  H04N19/105 ,  H04N19/139 ,  H04N19/42 ,  H04N19/423 ,  H04N19/50 ,  H04N19/51 ,  H04N19/523 ,  H04N19/57 ,  H04N19/59 ,  H04N7/32

Abstract: PURPOSE: To provide a motion vector extracting device which can calculate a motion vector at high speed in a simple circuit configuration. CONSTITUTION: An interpolation circuit calculates at least more than one interpolated pixel data positioned between two pixels by combining delayed pixel data from 1st-5th pixel delay elements 80, 82, 84, 86 and 88 with the pixel data of previous frames. 6th-9th pixel delay elements 92, 94, 96 and 98 generate current frame pixel data arranged rectangular by delaying the pixel data of a current frame. 1st-9th variation detection parts 100, 102, 104...116 respectively calculate average differential components corresponding to respective current frame pixel data by subtracting the interpolated pixel data in the interpolation circuit 90 from the current frame pixel data in the 6th-9th pixel delay elements 92, 94, 96 and 98. A comparator 118 detects the moving amount of pixels by mutually comparing the average differential components from the 1st-9th variation detection parts 100, 102, 104...116.