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公开(公告)号:JPH09163370A
公开(公告)日:1997-06-20
申请号:JP20584896
申请日:1996-08-05
Applicant: KOREA ELECTRONICS TELECOMM
Inventor: KIN KENSHIYU , KIN SHICHIYUU
IPC: H04N7/24 , G06T9/00 , H03M7/30 , H04N1/41 , H04N19/423 , H04N19/60 , H04N19/625 , H04N19/93 , H04N7/30
Abstract: PROBLEM TO BE SOLVED: To accelerate operating speed by composing a circuit only of a circuit using the regularity of scanning address patterns. SOLUTION: A sequential address generating part 21 inputs a start signal, clock signal and control signal and generates sequential addresses. A scanning address generating part 22 inputs a start signal, a clock signal and a control signal and generates a zigzag scanning address signal and an alternate scanning address signal. Based on the control signal, the 1st and the 2nd multiplexers 23 select the respective address signals from both address generating parts 21 and 22. A latch part 24 outputs the selected address signal while controlling timing.
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公开(公告)号:JPH09259115A
公开(公告)日:1997-10-03
申请号:JP29170596
申请日:1996-11-01
Applicant: KOREA ELECTRONICS TELECOMM
Inventor: KIN KENSHIYU , CHIYOU JIYUNKA , KEN YOSHIHIRO
Abstract: PROBLEM TO BE SOLVED: To convert respective inputted data into bit-serial data and speedily perform transposing operation for a matrix by storing respective registers with K/N-bit data selected by an output multiplexer module means, and then integrating N K/N-bit data into one data and outputting it as K-bit data. SOLUTION: A bit-serial transposing module means 12 selects and outputs shifted K/N-bit data, outputted by an input shift register module means 11, with a switching control signal. The output multiplexer module means 13 selects and outputs the K/N-bit data, outputted by the bit-serial transposing module means 12, by respective multiplexers. An output register module means 14 stores the respective registers with the K/N-bit data selected by the output multiplexer module means 13, and then integrates N K/N-bit data into one data, which is outputted as K-bit data.
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