公开(公告)号：JP2003142420A

公开(公告)日：2003-05-16

申请号：JP2002195126

申请日：2002-07-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE SEONG-JAE ,  CHO WON-JU ,  PARK KYOUNG WAN

IPC: H01L21/265 ,  H01L21/22 ,  H01L21/225 ,  H01L21/3115 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit equipped with a shallow junction. SOLUTION: A diffusion preventing film pattern 12 is formed on a semiconductor substrate 10, an SOG film doped with impurities is formed on the semiconductor substrate 10, and impurity ions are additionally implanted into the SOG film by a plasma ion implantation method to increase the SOG film in impurity concentration. Then, the impurities are diffused into the semiconductor substrate by rapid heat treatment by a solid-state diffusion method for the formation of a shallow junction. In this case, impurity concentration is precisely controlled by a plasma ion implantation method, but impurity ions are not implanted directly into the semiconductor substrate, so that the crystalline structure of the substrate is not damaged. Furthermore, if this method is applied after a gate electrode is formed, an LDD region and a source/drain extended region are formed in a self-aligned manner.

公开(公告)号：JP2002299636A

公开(公告)日：2002-10-11

申请号：JP2001392751

申请日：2001-12-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： CHO WONJU ,  LEE SEONG JAE ,  PARK KYOUNG WAN

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a high drive current by forming a fine channel and shallow source and drain of nm order size by utilizing a heavily doped silicon layer of a source and drain junction without separate lithographic process as a diffusion source and increasing an effective width of the channel in the same area. SOLUTION: An ultrafine MOS transistor comprises an SOI substrate including a single crystal substrate 10, an oxide film 20 formed on the substrate 10 and a first single crystal silicon layer formed on the film 20, a first silicon conductive layer 31 formed by heavily doping the first single crystal silicon layer, a source junction 80, channel 41 and drain junction 90 formed on the first silicon conductive layer 31, a gate insulating film 70 formed at the first silicon conductive layer 31, the source/drain junction and channel, a second silicon conductive layer formed at the drain junction, and a gate electrode 101 formed at a sidewall of the vertical channel.

公开(公告)号：JP2003163224A

公开(公告)日：2003-06-06

申请号：JP2002191424

申请日：2002-06-28

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE SEONG-JAE ,  CHO WON-JU ,  PARK KYOUNG WAN

IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/265 ,  H01L21/334 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a MOS transistor having shallow source/drain junction regions. SOLUTION: A diffusion source film is formed on a semiconductor substrate 10 where gate patterns 18 are formed and then the same type or different type of impurities are implanted into the diffusion source film several times at different implant angles. As a result, the impurity concentration of the diffusion source film can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate 10 does not occur and thus dislocation does not occur. Further, impurities contained in the diffusion source film having a nonuniform impurity concentration are diffused into the semiconductor substrate 10 by a solid phase diffusion method. Thus, the shallow source/drain junction regions composed of LDD regions and highly doped source/drain regions are formed by a self-alignment method. COPYRIGHT: (C)2003,JPO