公开(公告)号：JPH08186124A

公开(公告)日：1996-07-16

申请号：JP31536394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/732

Abstract: PURPOSE: To enhance integration of an element while simplifying the process by forming the base at an etched part of an insulation film through the use of an SEG step, forming a side wall film defining an emitter region on the side face of a nitride film, forming a conductive emitter layer in the emitter region thus defined and then interconnecting the electrodes. CONSTITUTION: Integration of element is enhanced through the use of a step for making a shallow trench and the number of trenches is decreased by thermally oxidizing the collector region 23 on the outside of an active region such that the collector region 23 has a depth similar to that of the shallow trench. Unnecessary regions are then removed from an isolation film and an insulation film defining the active region thus reducing the size of element and the parasitic capacitance between the subcollector and the board. Since the thickness of insulation film can be adjusted arbitrarily to the order of the thickness of shallow trench, parasitic capacitance of metal interconnection can be decreased. Furthermore, the process is simplified by eliminating the trench isolation step and the SEG step for growing interconnect polisilicon arsenide while self-aligning the emitter, base and collector.

公开(公告)号：JPH08186165A

公开(公告)日：1996-07-16

申请号：JP31481394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/737

Abstract: PURPOSE: To obtain a method for producing an isolated SOI(Silicon on Insulator) in which the reliability is enhanced by planarizing a thin film completely through a simple process regardless of the pattern density or the uniformity of the surface while facilitating control of the thickness of each thin film constituting the substrate. CONSTITUTION: The SOI substrate comprises a second insulation layer 23b formed on the entire surface of a substrate 27 bonded directly thereto, a first insulation layer 23a formed on the second insulation layer 23b and planarized, and an active layer 31 isolated through the first insulation layer 23a.

公开(公告)号：JPH08186122A

公开(公告)日：1996-07-16

申请号：JP31342494

申请日：1994-12-16

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To realize up/down motion mode by isolating an active region through the use of a simple photolithography and eliminating the trench isolation step which causes lowering of the extent of integration and deterioration of the element thereby obtaining a super self-aligned vertical structure of emitter, base and collector regions. CONSTITUTION: Trench isolation step is eliminated by isolating an active region through the use of simple photolithography thus simplifying the process and improving the extent of integration. Since the emitter, base and collector regions 34, 32, 31 have self-aligned vertical structure, an up/down motion mode can be realized. Size of the element and the parasitic capacitance between a subcollector and board can be reduced by removing the unnecessary region of an isolation film and an insulation defining the active region. Furthermore, an ultrathin film base and an interconnect polysilicon layer are grown entirely in a SEG, thickness of the insulation layer is limited and since thin films 23, 24, 25, 26 are utilized, parasitic capacitance between metal interconnections is reduced.