公开(公告)号：JPH08186124A

公开(公告)日：1996-07-16

申请号：JP31536394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/732

Abstract: PURPOSE: To enhance integration of an element while simplifying the process by forming the base at an etched part of an insulation film through the use of an SEG step, forming a side wall film defining an emitter region on the side face of a nitride film, forming a conductive emitter layer in the emitter region thus defined and then interconnecting the electrodes. CONSTITUTION: Integration of element is enhanced through the use of a step for making a shallow trench and the number of trenches is decreased by thermally oxidizing the collector region 23 on the outside of an active region such that the collector region 23 has a depth similar to that of the shallow trench. Unnecessary regions are then removed from an isolation film and an insulation film defining the active region thus reducing the size of element and the parasitic capacitance between the subcollector and the board. Since the thickness of insulation film can be adjusted arbitrarily to the order of the thickness of shallow trench, parasitic capacitance of metal interconnection can be decreased. Furthermore, the process is simplified by eliminating the trench isolation step and the SEG step for growing interconnect polisilicon arsenide while self-aligning the emitter, base and collector.

公开(公告)号：JPH05347317A

公开(公告)日：1993-12-27

申请号：JP34485591

申请日：1991-12-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU TETSUJIYUN ,  CHIN KIKAN ,  MOU SEIZAI ,  YOU TENKIYOKU ,  SAI EIKEI ,  KIYOU CHINEI ,  RI KEIKOU ,  RI SHINHI ,  KIN DOUCHIN

IPC: H01L29/812 ,  H01L21/285 ,  H01L21/338

Abstract: PURPOSE: To improve a resistance characteristic by using a double-layered heat-resistant gate obtained by forming a heat-resistant junction material on the surface of a GaAs substrate and forming a metal having a low resistance on the junction material. CONSTITUTION: N-type impurities 121a are ion-implanted into an active-layer region of a GaAs substrate 121 with the pattern of a photosensitive film 124 as a mask. Next, the photosensitive film 124 is removed, and a silicon layer 122 and a metallic layer 123 are sequentially deposited. Then, a double layer comprising a metal layer 123a and a silicon layer 122a is formed by an etching process. Then, highly concentrated n-type impurities 121b are ion-implanted into a source/drain region, within the active region of the double layer. After the implantation, heat treatment is performed to cause a chemical reaction. By this treatment, a part of the metallic layer 123 in contact with the silicon layer 122 changes into a metallic silicide layer 125. Then, an ohmic electrode 126 is formed, and the device is completed. Thus, the gate has a low resistance.

公开(公告)号：JPH08186165A

公开(公告)日：1996-07-16

申请号：JP31481394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/737

Abstract: PURPOSE: To obtain a method for producing an isolated SOI(Silicon on Insulator) in which the reliability is enhanced by planarizing a thin film completely through a simple process regardless of the pattern density or the uniformity of the surface while facilitating control of the thickness of each thin film constituting the substrate. CONSTITUTION: The SOI substrate comprises a second insulation layer 23b formed on the entire surface of a substrate 27 bonded directly thereto, a first insulation layer 23a formed on the second insulation layer 23b and planarized, and an active layer 31 isolated through the first insulation layer 23a.

公开(公告)号：JPH0645361A

公开(公告)日：1994-02-18

申请号：JP34486191

申请日：1991-12-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU TETSUJIYUN ,  CHIN KIKAN ,  MOU SEIZAI ,  YOU TENKIYOKU ,  SAI EIKEI ,  KIYOU CHINEI ,  RI KEIKOU ,  RI SHINHI ,  KIN DOUCHIN

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/338 ,  H01L29/812

Abstract: PURPOSE: To allow silicon ions within an evaporated silicon thin film to the diffused into a substrate, even by implanting small amounts of low-energy ions and by heat treatment. CONSTITUTION: A method of manufacturing a GaAs metal-semiconductor field effect transistor involves the steps of: forming a silicon layer 2 on a GaAs substrate 1, forming a first photoresist pattern 3 on the silicon layer 2 using a known image inversion method to define an ohmic contact for source/drain electrodes and etching a silicon layer portion excluding the ohmic contact using photolithography, defining a channel region by forming a second photoresist pattern 4 on the substrate 1 after the first photoresist pattern 3 has been removed, and forming a channel region 5 by implanting a prescribed amount of silicon ions Si into the substrate 1, using the second photoresist pattern 4 as a mask.

公开(公告)号：JPH08186122A

公开(公告)日：1996-07-16

申请号：JP31342494

申请日：1994-12-16

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To realize up/down motion mode by isolating an active region through the use of a simple photolithography and eliminating the trench isolation step which causes lowering of the extent of integration and deterioration of the element thereby obtaining a super self-aligned vertical structure of emitter, base and collector regions. CONSTITUTION: Trench isolation step is eliminated by isolating an active region through the use of simple photolithography thus simplifying the process and improving the extent of integration. Since the emitter, base and collector regions 34, 32, 31 have self-aligned vertical structure, an up/down motion mode can be realized. Size of the element and the parasitic capacitance between a subcollector and board can be reduced by removing the unnecessary region of an isolation film and an insulation defining the active region. Furthermore, an ultrathin film base and an interconnect polysilicon layer are grown entirely in a SEG, thickness of the insulation layer is limited and since thin films 23, 24, 25, 26 are utilized, parasitic capacitance between metal interconnections is reduced.

公开(公告)号：JPH08148554A

公开(公告)日：1996-06-07

申请号：JP30794694

申请日：1994-12-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  KIYOU CHINEI

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

Abstract: PURPOSE: To form a field region which is free of a bird's beak by forming a trench beside an active region, filling an insulating material into the trench and forming an oxide film by performing a thermal oxidation on a substrate. CONSTITUTION: On a semiconductor substrate 51, a pad oxide film 52, a polysilicon oxide layer 53, a silicon oxide film 54, a nitride film 55, and a silicon oxide film 56 are formed in sequence. Thereafter, etchings are performed on the silicon oxide film 56, the nitride film 55, the nitride oxide in an inactive region in sequence. Subsequently, a side face nitride film 57 is formed on a side face of the active region, and an insulating layer 58 is formed on the upper portion of the exposed polysilicon layer 53 in the inactive region. Then, the side face nitride film 57 is opened. By making use of this pattern, an etching is performed on a given portion of the substrate 51 followed by filling of an insulating material, so as to form a trench 59 which is filled with the insulating material. Subsequently, the oxide film 55 in the active region and the pad oxide film 52 in the inactive region are respectively exposed, and thereafter a thermal oxidation is performed on the substrate to form a field oxide film 50 which is free of a bird's beak.