公开(公告)号：JPH08186124A

公开(公告)日：1996-07-16

申请号：JP31536394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/732

Abstract: PURPOSE: To enhance integration of an element while simplifying the process by forming the base at an etched part of an insulation film through the use of an SEG step, forming a side wall film defining an emitter region on the side face of a nitride film, forming a conductive emitter layer in the emitter region thus defined and then interconnecting the electrodes. CONSTITUTION: Integration of element is enhanced through the use of a step for making a shallow trench and the number of trenches is decreased by thermally oxidizing the collector region 23 on the outside of an active region such that the collector region 23 has a depth similar to that of the shallow trench. Unnecessary regions are then removed from an isolation film and an insulation film defining the active region thus reducing the size of element and the parasitic capacitance between the subcollector and the board. Since the thickness of insulation film can be adjusted arbitrarily to the order of the thickness of shallow trench, parasitic capacitance of metal interconnection can be decreased. Furthermore, the process is simplified by eliminating the trench isolation step and the SEG step for growing interconnect polisilicon arsenide while self-aligning the emitter, base and collector.

公开(公告)号：JPH08186165A

公开(公告)日：1996-07-16

申请号：JP31481394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/737

Abstract: PURPOSE: To obtain a method for producing an isolated SOI(Silicon on Insulator) in which the reliability is enhanced by planarizing a thin film completely through a simple process regardless of the pattern density or the uniformity of the surface while facilitating control of the thickness of each thin film constituting the substrate. CONSTITUTION: The SOI substrate comprises a second insulation layer 23b formed on the entire surface of a substrate 27 bonded directly thereto, a first insulation layer 23a formed on the second insulation layer 23b and planarized, and an active layer 31 isolated through the first insulation layer 23a.

公开(公告)号：JPH08186125A

公开(公告)日：1996-07-16

申请号：JP31537194

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  CHIYOU TOKUKOU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  KEN GOJIYUN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/732

Abstract: PURPOSE: To obtain a method for fabricating a heterojunction bipolar transistor in which the operational characteristics can be improved by decreasing the parasitic resistance of the base significantly through the use of a thin metal silicide film and varying the thickness of the film. CONSTITUTION: An Si substrate is heavily doped with impurity ions to form a conductive collector 21 and then a single crystal layer 22 of the collector, an isolation oxide and a collector sinker 24 are formed thereon. Subsequently, an SiGe base layer 25 is epitaxially grown on the entire surface of the substrate and an oxide is deposited and patterned. Ions are then implanted into the exposed external base region using the oxide as a mask before the mask oxide is removed. Thereafter, a thin TiSi film 26 for the base electrode is deposited by sputtering only above the base region and the thickness of the film can be diversified. Subsequently, a capping oxide is deposited on the thin film followed by deposition of an oxide 27 for isolating emitter and base over the entire surface of the substrate. In order to open a collector sinker, the oxide, the thin electrode film and the base layer are patterned and a side wall oxide 28 is deposited. Finally, the isolation oxide is etched partially to form an emitter layer 29.

公开(公告)号：JPH08186122A

公开(公告)日：1996-07-16

申请号：JP31342494

申请日：1994-12-16

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To realize up/down motion mode by isolating an active region through the use of a simple photolithography and eliminating the trench isolation step which causes lowering of the extent of integration and deterioration of the element thereby obtaining a super self-aligned vertical structure of emitter, base and collector regions. CONSTITUTION: Trench isolation step is eliminated by isolating an active region through the use of simple photolithography thus simplifying the process and improving the extent of integration. Since the emitter, base and collector regions 34, 32, 31 have self-aligned vertical structure, an up/down motion mode can be realized. Size of the element and the parasitic capacitance between a subcollector and board can be reduced by removing the unnecessary region of an isolation film and an insulation defining the active region. Furthermore, an ultrathin film base and an interconnect polysilicon layer are grown entirely in a SEG, thickness of the insulation layer is limited and since thin films 23, 24, 25, 26 are utilized, parasitic capacitance between metal interconnections is reduced.

公开(公告)号：JPH08148554A

公开(公告)日：1996-06-07

申请号：JP30794694

申请日：1994-12-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  KIYOU CHINEI

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

Abstract: PURPOSE: To form a field region which is free of a bird's beak by forming a trench beside an active region, filling an insulating material into the trench and forming an oxide film by performing a thermal oxidation on a substrate. CONSTITUTION: On a semiconductor substrate 51, a pad oxide film 52, a polysilicon oxide layer 53, a silicon oxide film 54, a nitride film 55, and a silicon oxide film 56 are formed in sequence. Thereafter, etchings are performed on the silicon oxide film 56, the nitride film 55, the nitride oxide in an inactive region in sequence. Subsequently, a side face nitride film 57 is formed on a side face of the active region, and an insulating layer 58 is formed on the upper portion of the exposed polysilicon layer 53 in the inactive region. Then, the side face nitride film 57 is opened. By making use of this pattern, an etching is performed on a given portion of the substrate 51 followed by filling of an insulating material, so as to form a trench 59 which is filled with the insulating material. Subsequently, the oxide film 55 in the active region and the pad oxide film 52 in the inactive region are respectively exposed, and thereafter a thermal oxidation is performed on the substrate to form a field oxide film 50 which is free of a bird's beak.

公开(公告)号：JPH0669219A

公开(公告)日：1994-03-11

申请号：JP13751493

申请日：1993-06-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KITOU ,  GU YOUSHIYO ,  KAN TAIGEN ,  GU CHINKON

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To improve the integration of a logic circuit by constituting a bipolar device as an upward-structure type, including an isolation oxide film, filled in a trench formed in a semiconductor substrate. CONSTITUTION: An n -embedded layer 2 is formed on a silicon substrate 1, on which layer an emitter is formed. A silicon layer 3 is formed on the n - embedded layer 2 which a low-temperature growing method, on which layer a substantial base is formed. After completion of the formation of a field oxide film 9, there are formed on the semiconductor substrate 1 the sequence, an N -polycrystalline silicon 10, a silicide 11, a low-temperature deposited oxide film 12, and a polycrystalline silicon layer 13. In succession, after an N - polycrystalline silicon electrode and a collector region are defined with a fine pattern formation method the layers 10 to 13 are selectively removed with a dry etching method. Operating voltage and a switching speed of an IIL circuit are improved by making equal the upward operating characteristic and downward operating characteristic of the bipolar device. Hereby, in the case of an ECL circuit, integration is enhanced sharply while keeping speed performance.