DEVICE FOR RECEIVING DATA FROM TELEPHONE LINE

    公开(公告)号:JPH11298592A

    公开(公告)日:1999-10-29

    申请号:JP4704699

    申请日:1999-02-24

    Abstract: PROBLEM TO BE SOLVED: To process call related information on the high voltage side of a telephone circuit inside a digital signal path by digitizing an analog signal from a telephone line while using the sigma/delta(Σ/Δ) or analog/digital(A/D) converter of low-power CODEC, to which power is supplied from a line, filtering and decoding digitized data. SOLUTION: A audio CODEC 104 is a Δ/Σ audio CODEC capable of operating in a reduced power mode for operating a Σ/Δor A/D converter 140 of switchable dimension number while using power extracted from a telephone line. By arranging the audio CODEC 104 capable of digitally processing and demodulating the call related information on the side of the line, costs for the reception circuit of the call related information (caller ID) can be reduced and the call related information can be received while using power from the line side.

    CURRENT CONTROLLER
    2.
    发明专利

    公开(公告)号:JPH11239233A

    公开(公告)日:1999-08-31

    申请号:JP31709898

    申请日:1998-11-09

    Abstract: PROBLEM TO BE SOLVED: To control the current through a DC terminal device by supplying a control voltage in order to control a voltage controlled current source(VCCS) as the function of a prescribed voltage. SOLUTION: When a control circuit 14 is in a fixed impedance mode, a chip/ring DC voltage received from a line filtered by a low-pass filter 52 is impressed to a multiplier 58. At this multiplier 58, the voltage is amplified by a DC terminal correction coefficient from a DC terminal correction coefficient 56. In the fixed impedance mode, the control. voltage for a VCCS 12 on an output line 40 is the corrected appropriately proportional value of a chip/ring voltage received through the line. When the control circuit 14 is in a fixed current mode, the fixed DC voltage is loaded through a switch 60 to the output line 40. Therefore, the DC control voltage impressed to the output line 40 for controlling the VCCS 12 is fixed.

    SEPARATE TYPE AUDIO CODEC DEVICE
    3.
    发明专利

    公开(公告)号:JPH11168530A

    公开(公告)日:1999-06-22

    申请号:JP25283698

    申请日:1998-09-07

    Abstract: PROBLEM TO BE SOLVED: To speedily start an audio codec device from a low power mode by directly sending a signal to the function block of an analog sub-system in a low power mode state from a peripheral device and starting a wake-up procedure in the analog sub-system and/or a controller sub-system. SOLUTION: An interruption sensor 186 directly inputs a ring detection signal 196 detected by a wire interface 194 connected to a telephone line 192 to the interruption controller 182 of the AC analog sub-system 104 through an optical isolator 197. An interruption controller 182 sets an interruption register 180 in an enable state. A system clock signal 310 passes through a second and gate 174, counts up a counter 122, sets a wake-up interruption register 126 in the enable state, sets a controller 102 in the enable and sets the remaining part of the AC analog sub-system it the wake-up state.

    LINE TRANSPONDER, METHOD AND SYSTEM FOR CHECKING TELEPHONE LINE, AND METHOD AND SYSTEM FOR PROVIDING SERVICE INFORMATION

    公开(公告)号:JP2002033825A

    公开(公告)日:2002-01-31

    申请号:JP2001014222

    申请日:2001-01-23

    Abstract: PROBLEM TO BE SOLVED: To provide an identification device and method that can be used by a telephone line engineer to identify incorporated services by checking a telephone line at a site. SOLUTION: A tuning circuit with a specific resonance frequency replies a test signal with a specific resonance frequency injected to the line by means of a stimulation signal, and a modulator modulates the simulation signal when the text signal exists. By injecting a questionnaire test signal including a specific frequency to a telephone line, the simulation signal from the tuning circuit is detected in response to the specific frequency. A telephone line to which a test signal including a specific frequency component is injected is monitored, and when test signal is detected on the telephone line, the characteristics of the test signal with the specific frequency is enhanced.

    METHOD AND DEVICE FOR ADJUSTING DC LINE CURRENT IN TELEPHONE LINE

    公开(公告)号:JP2001103126A

    公开(公告)日:2001-04-13

    申请号:JP2000249208

    申请日:2000-08-21

    Abstract: PROBLEM TO BE SOLVED: To eliminate the occurrence of an error due to a DC offset in an analog circuit caused when a DC line current of a telephone line is adjusted. SOLUTION: The method and the system are to adjust a DC line current in a telephone line and to reduce the quantity of errors introduced to a system. Compensating a DC error component introduced by an A/D converter having a DC offset can reduce the error. A software program can limit the DC error according to predetermined parameters through digital control of the DC offset. The predetermined parameters are selected to cover specifications in various countries in place of a switch controlling resistors and capacitors. Furthermore, even when a standard of a country is changed, the software program can cope with the change in place of replacing components or redesigning a printed circuit board.

    SYNCHRONOUS DATA TRANSFER PROTOCOL WORKING VIA HIGH VOLTAGE INTERFACE

    公开(公告)号:JP2000232439A

    公开(公告)日:2000-08-22

    申请号:JP36358499

    申请日:1999-12-22

    Abstract: PROBLEM TO BE SOLVED: To decrease the number of signal lines of a synchronous serial interface by putting a preamble code word into a data stream to be transmitted and detecting the preamble code word contained in the data stream via a synchronous preamble detection module. SOLUTION: A controller 100 stops intentionally the operation of a clock source 130 for a prescribed time to start the resynchronization and puts a preamble code word into a transmission data stream 116. A clock absence timer 132 of the controller 100 has a self-monitoring function to decide how long the controller 100 has stopped the output operation of the source 130 onto a clock signal line 110. Then a preamble inserting module 134 puts a preamble code word into a time slot after a satisfactory time elapses from a point of time when the clock received from a CODEC 106 is held.

    DEVICE TRANSMITTING COMBINED DATA/CLOCK SIGNAL

    公开(公告)号:JPH11317775A

    公开(公告)日:1999-11-16

    申请号:JP1568599

    申请日:1999-01-25

    Abstract: PROBLEM TO BE SOLVED: To decrease the number of communication lines needed for a serial interface between circuits while minimizing the jitters of a data clock recovered at a reception terminal. SOLUTION: A receiver system has a receiver 310 which receives a combined clock/data signal generated by combining a clock and data through 1-bit sigma data encoding and an edge detector 312 which detects an edge of the combined clock/data signal. A phase-locked loop 314 makes a lock according to the signal from the edge detector 312. A gate 318 derives the clock signal from the combined clock/data signal and a divider 320 divides the derived clock signal to generate a recovered clock signal 330 which corresponding to the bit rate of the original signal. A latch 322 driven by the phase-locked loop 314 derives the data signal from the combined clock/data signal.

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