Abstract:
A conductive, light-absorbing baseplate for use in a field emission display is disclosed. The interior surface of the baseplate is coated with a praseodymium-manganese oxide layer having a resistivity that does not exceed 1 x 10 OMEGA .cm. A field emission display is also disclosed which comprises the conductive, light-absorbing baseplate, as well as processes for manufacturing the baseplate, field emission display and the conductive, light-absorbing praseodymium-manganese oxide material used to coat the baseplate.
Abstract:
An improved method for sharpening emitter sites for cold cathode field emission displays (FEDs) includes the steps of: forming a projection on a baseplate; growing an oxide layer on the projection using a low temperature oxidation process; and then stripping the oxide layer. Preferred low temperature oxidation processes include: wet bath anodic oxidation, plasma assisted oxidation and high pressure oxidation. These low temperature oxidation processes grow an oxide film using a consumptive process in which oxygen reacts with a material of the projection. This permits emitter sites to be fabricated with less distortion and grain boundary formation than emitter sites formed with thermal oxidation. As an example, emitter sites can be formed of amorphous silicon. In addition, low temperature materials such as glass can be used in fabricating baseplates without the introduction of high temperature softening and stress.
Abstract:
A semiconductor device for use in field emission displays includes a substrate (30) formed from a semiconductor material, glass, soda lime, or plastic. A first layer of a conductive material (28) is formed on the substrate. A second resistive layer of microcrystalline silicon (32) is formed on the first layer. This layer has characteristics that do not fluctuate in response to conditions that vary during the operation of the field emission display, particularly the varying light intensity from the emitted electrons or from the ambient. One or more cold-cathode emitters (34) are formed on the second layer.
Abstract:
A system for sampling an analog or digital data signal at a relatively high rate utilizing relatively slow circuitry. The system (40) includes several sample and hold circuits (42 - 50), each of which receive the data signal. The sample and hold circuits (42- 50) are clocked by respective clock signals ( PHI 1... PHI n)that are at the same frequency but equally phased apart from each other. Thus, the sample and hold circuits take samples of the data signal at times that are equally spaced apart from each other. Each of the sample and hold circuits is connected to a series of shift registers (62 - 70) that are clocked at the same frequency as the clock used to clock the sample and hold circuit to which they are connected. The shift registers operate to sequentially store samples (S1... Sn) obtained by their respective sample and hold circuit. The output of the shift registers (82 - 90) may be applied to the column drivers of a conventional matrix display.
Abstract:
A process is provided for manufacturing high-purity phosphors having utility in field emission displays. The high-purity phosphor is a host lattice infiltrated by a dopant that activates luminescent properties therein. The lattice and dopant are initially milled together to reduce their average particle size while simultaneously achieving complete mixing between the lattice and the dopant. The resulting mixture is maintained free of a flux or substantially any other treatment agent capable of contaminating the phosphor and placed in a heating vessel formed from a substantially impervious contaminant-free material. The mixture is heated to a high temperature effectuating thorough infiltration of the dopant into the lattice structure. The use of an impervious contaminant-free heating vessel and the exclusion of flux or other treatment agents from the mixture avoids undesirable contamination and undue particle size growth of the phosphor product during the manufacture thereof. Accordingly, product is a high-purity phosphor having a small average particle size, yet exhibiting sufficient luminescent efficiencies for utility in field emission displays as a luminescent coating for the anode screen.
Abstract:
A field emission display having emitters controlled by an integrated driving circuit. The field emission display includes a charge shield positioned above exposed areas of the substrate to protect driving circuitry integrated into the substrate. The charge shield is a conductive layer within an insulative layer covering the driving circuit. The charge shield is connected to ground or to a low reference potential to bleed away current within the insulative layer, thereby preventing drifting charges from affecting the electrical response of the integrated driving circuit. The charge shield also terminates electric fields within the insulative layer to reduce the effect on the integrated driving circuit of dynamic variations in surface charge. Electrical characteristics of the driving circuit thus remain constant, reducing variations in the current supplied to the emitters, thereby reducing variations in the intensity of light emitted by the display.
Abstract:
According to two aspects of the invention, a FED and a process for making a FED are provided which effectuate more accurate and efficient sealing between a faceplate and a backplate assembly, with more accurate and efficient sealing between the faceplate (10) and cathode member (12). The FED is made according to a process comprising: aligning the faceplate and the cathode member; disposing an adhesive (16) between the faceplate and the cathode member; pressing the faceplate and the cathode member together; disposing a frit seal (18) between the faceplate and the backplate assembly; and heating the frit seal to a temperature sufficient to cause the frit to seal.
Abstract:
A field emission display device includes a baseplate having a set of field-induced electron emitters for each pixel in a display. Each set includes a plurality of emitters each carried by a supporting substrate and disposed within a respective aperture in an insulating layer deposited on the surface of the substrate. A conductive layer is deposited on the insulating layer peripherally about the apertures. A plurality of emitter conductors are each operatively coupled to the emitters of one of the sets of emitters. A conductive voltage applied to the conductive layer and a source voltage applied to one of the emitter conductors causes the emitters coupled to the emitter conductor to each emit an electron emission. The display device also includes a faceplate having a transparent viewing layer positioned in a parallel spaced-apart relationship with the baseplate. An anode is deposited on a planar surface of the viewing layer opposite the sets of emitters. A luminescent layer has a plurality of localized portions each deposited on the anode opposite one of the sets of emitters so that an anode voltage applied to the anode will direct any electron emissions from the emitters toward the localized portions of the luminescent layer. Finally, a plurality of focusing electrodes each comprising a conductive strip are deposited on the planar surface of the viewing layer around the periphery of a respective localized portion of the luminescent layer substantially opposite the respective set of emitters of the localized portion so that a focusing electrode voltage which is less than the anode voltage applied to the focusing electrodes will focus these electron emissions on the localized portions of the luminescent layer.
Abstract:
A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.
Abstract:
A method of phase shift lithography includes forming a chromeless phase shift reticle (10) with a pattern of parallel, spaced phase shifters (14). An exposure energy (22) is directed through the phase shift reticle (10) and onto a target (18) having a layer resist (23) formed thereon. Following an initial exposure, the phase shift reticle (10) is rotated and the resist (23) is exposed a second time. The resist (23) is then developed to form features in areas of resist that have not been exposed. These areas correspond to the projected points of intersection (34) of the phase shifters (14). Using a positive tone resist, solid resist features are formed. These solid features can be used to form a mask (46) for etching the target (18) to form field emitter sites (38) for a field emission display. Using a negative tone resist, open areas are formed in the resist (23) and can be used to deposit a material on the substrate such as contacts (56) on a semiconducting substrate (48). The method of the invention can also be implemented using two different reticles (10) with intersecting patterns or using a single reticle (10) having intersecting phase shift areas.