公开(公告)号：EP3114706A1

公开(公告)日：2017-01-11

申请号：EP15708673.7

申请日：2015-02-26

Applicant: Qualcomm Incorporated

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/426 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/18 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0094

Abstract: A substrate includes a plurality of vias (210) that are lined with dielectric polymer (215) having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal (220) into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract translation: 衬底包括多个具有基本上均匀厚度的介电聚合物的通孔。 这种基本上均匀的厚度提供在每个介质聚合物层衬里的通孔内的内腔，其基本上位于通孔内。 随后，对于每个介质聚合物层衬里的通孔，随后将金属沉积到管腔中，由此提供具有基本中心的金属导体的导电通孔。

公开(公告)号：WO2016148879A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/019948

申请日：2016-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  LEE, Jae Sik

IPC: H05K1/18 ,  H01G4/00 ,  H01G4/33 ,  H01G4/232 ,  H01L23/522 ,  H01L23/64 ,  H01L23/00

CPC classification number: H01L21/4846 ,  H01G4/33 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4661

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract translation: 扇出晶片级封装结构可以包括多层再分配层（RDL）。 多层RDL可以被配置为与嵌入式电容器的端子耦合。 根据所选择的等效串联电阻（ESR）控制模式，多层RDL可以包括具有比多层RDL的其它部分更少的层的部分。

公开(公告)号：WO2016123115A1

公开(公告)日：2016-08-04

申请号：PCT/US2016/014939

申请日：2016-01-26

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung

IPC: H01L25/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package.

Abstract translation: 公开了一种用于形成封装封装（POP）结构的方法。 该方法包括将柱放置在第一集成电路（IC）封装上，使得设置在柱的第一表面上的焊料涂层位于第一IC封装的柱和第二表面之间。 柱沿模具的特定轴线放置在与模具相距一定距离处。 特定轴线基本上平行于第二表面。 第一个IC封装包括裸片。 该方法还包括在第二IC封装和第一IC封装之间经由柱和焊料凸块形成导电路径。 焊料凸块设置在柱和第二IC封装之间。

公开(公告)号：WO2014138285A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/020868

申请日：2014-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： LISK, Durodami Joscelyn ,  RAMACHANDRAN, Vidhya ,  LEE, Jae Sik

IPC: H01L25/10

CPC classification number: H01L23/5384 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/1403

Abstract: A via-enabled package-on-package circuit includes a first package (316) including a first package die (310) having a plurality of through substrate vias (TSVs) (322). The TSVs are configured to carry the input/output signaling for at least one second package die (315).

Abstract translation: 通孔启用封装封装电路包括第一封装（316），其包括具有多个贯穿衬底通孔（TSV）（322））的第一封装管芯（310）。 TSV被配置为承载用于至少一个第二封装管芯（315）的输入/输出信号。

公开(公告)号：WO2017139285A1

公开(公告)日：2017-08-17

申请号：PCT/US2017/016864

申请日：2017-02-07

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook

IPC: H01L23/538

CPC classification number: H01L23/5387 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49833 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1815

Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

Abstract translation: 一些特征涉及包括第一集成电路（IC）封装，柔性连接器和第二集成电路（IC）封装的集成器件。 第一集成电路（IC）封装包括第一裸片，多个第一互连以及封装第一裸片的第一介电层。 该柔性连接器耦合到第一集成电路（IC）封装。 柔性连接器包括第一介电层和互连。 第二集成电路（IC）封装耦合到柔性连接器。 第二集成电路（IC）封装包括第一电介质层和多个第二互连。 第一集成电路（IC）封装，第二集成电路（IC）封装和柔性连接器通过第一介电层的至少一部分（例如，连续部分）耦合在一起。 在一些实现中，柔性连接器包括伪金属层。

公开(公告)号：WO2016200604A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/033948

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/14 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Abstract translation: 封装封装（PoP）结构包括通过第一管芯和第二管芯之间的插入件电耦合到第一管芯和第二管芯的第一管芯，第二管芯和存储器件。 插入器包括在模具内形成的填充铜的通孔。

公开(公告)号：WO2016073790A1

公开(公告)日：2016-05-12

申请号：PCT/US2015/059336

申请日：2015-11-05

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L23/538

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：WO2017142640A1

公开(公告)日：2017-08-24

申请号：PCT/US2017/012608

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H01L24/14 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects (125) couple to pads (111) on an encapsulated (135) die (105,110). The interconnects have a pad-facing surface that couples to a corresponding pad through a seed layer (145). The seed layer does not cover the sidewalls of the interconnects.

Abstract translation: 提供了扇出晶圆级工艺集成电路，其中多个互连（125）耦合到封装（135）管芯（105,110）上的焊盘（111）。 互连件具有通过种子层（145）耦合到相应垫的面向垫的表面。 种子层不覆盖互连的侧壁。

公开(公告)号：WO2017034641A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/035895

申请日：2016-06-03

Applicant: QUALCOMM INCORPORATED

Inventor： GU, Shiqun ,  WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

Abstract translation: 集成器件封装包括第一管芯，第二管芯，耦合到第一管芯和第二管芯的封装部分，以及耦合到封装部分的再分配部分。 封装部分包括封装层，桥和第一通孔。 该桥至少部分地嵌入在封装层中。 桥被配置成为第一管芯和第二管芯之间的第一信号提供第一电路径。 第一个通道在封装层中。 第一个通道耦合到桥。 第一通孔和桥被配置为为第一管芯提供第二信号的第二电路径。 再分布部分包括至少一个电介质层，以及在电介质层中耦合到第一通孔的至少一个互连。

公开(公告)号：WO2016160283A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/021278

申请日：2016-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook

IPC: H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32137 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/381 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

Abstract translation: 集成电路（IC）封装结构可以包括衬底。 衬底可以包括半导体电桥，其具有直接位于衬底的面向第一半导体管芯和第二半导体管芯的表面上的第一表面。 半导体桥可以设置在延伸穿过衬底表面上的光敏层的空腔内。 半导体桥可以具有基本上与光敏层齐平的暴露的第二表面。 第一半导体管芯和第二半导体管芯由衬底支撑并通过半导体桥耦合在一起。