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    STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV
    4.
    发明公开
    STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV 审中-公开
    结构与方法通过基片A应变消除

    公开(公告)号：EP2820671A1

    公开(公告)日：2015-01-07

    申请号：EP13708323.4

    申请日：2013-02-26

    Applicant: Qualcomm Incorporated

    Inventor： RAMACHANDRAN, Vidhya ,  GU, Shiqun

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face. The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.

    SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE
    5.
    发明申请
    SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE 审中-公开
    降低PARASIIC电容的系统和方法

    公开(公告)号：WO2016160313A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/022200

    申请日：2016-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： GU, Shiqun ,  RAMACHANDRAN, Vidhya ,  HAU-RIEGE, Christine Sung-An ,  ZHU, John Jianhong ,  XU, Jeffrey Junhao ,  CHOI, Jihong ,  CHEN, Jun ,  YEAP, Choh Fei

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

    Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device includes a dielectric layer (114). The device includes first and second conductive structures (102, 104) and an etch stop layer (105) proximate to the dielectric layer. The etch stop layer defines first and second openings (109, 119) proximate to a region of the dielectric layer between the first and second conductive structures. The device includes first and second airgaps (107, 113) within the region. The device includes a layer of material (110) proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer covers the first and second airgaps.

    Abstract translation: 公开了减小寄生电容的装置和方法。 一种器件包括介电层（114）。 该器件包括靠近电介质层的第一和第二导电结构（102,104）和蚀刻停止层（105）。 蚀刻停止层限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口（109,119）。 该装置包括区域内的第一和第二气隙（107,113）。 该装置包括靠近蚀刻停止层（例如，在其上方，上方或上方）的材料层（110）。 靠近蚀刻停止层的材料层覆盖第一和第二气隙。

    STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV
    9.
    发明申请
    STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV 审中-公开
    用于菌株TSV的结构和方法

    公开(公告)号：WO2013130425A1

    公开(公告)日：2013-09-06

    申请号：PCT/US2013/027729

    申请日：2013-02-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAMACHANDRAN, Vidhya ,  GU, Shiqun

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face. The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.

    Abstract translation: 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 半导体管芯包括具有主动面的半导体衬底。 半导体衬底包括连接到有源面的导电层。 半导体管芯还包括仅通过衬底延伸的贯通衬底。 直通衬底通孔可以包括通过穿过衬底通孔的长度的基本上恒定的直径。 贯通基板通孔可以填充有导电填充材料。 半导体管芯还包括围绕贯穿衬底通孔的隔离层。 隔离层可以包括两部分：靠近衬底的有源面的凹陷部分，其能够缓和来自导电填充材料的应力，以及介电部分。 凹部的组成可以不同于电介质部分。

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