公开(公告)号：JP2000353091A

公开(公告)日：2000-12-19

申请号：JP2000134612

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  FEL BRUNO ,  DUCOUSSO LAURENT

IPC: G06F9/28 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a computer system in which both a superscaler mode and a VLIW mode are dealt with by instruction scheduling and data dependency between different instruction scan can be processed. SOLUTION: An instruction in a computer system is executed by plural parallel execution pipelines 13 to 16, checks 39 and 42 of dependency in the same row direction are supplied to the parallel pipelines 13 to 16, are executed between other instructions and, moreover, in response to the dependency in the same row direction to be detected, a control signal of a first or a second type is generated by depending upon whether or not the dependency can be released or not by activating a bypass or whether or not a temporary section is obtained for one of the pipelines.

公开(公告)号：JP2000330790A

公开(公告)日：2000-11-30

申请号：JP2000134618

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  FEL BRUNO ,  DUCOUSSO LAURENT

IPC: G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To process the data dependency between different instructions by making ineffective a dependency check between instructions in the left-right direction as to instructions of very long instruction word(VLIW) mode. SOLUTION: Instructions are held in a program memory 11, sent to a control unit 12, and supplied to parallel execution pipelines 13 to 16. An instruction is decoded by a decoder 82 and the output of a dependency check circuit 87 is sent to a left-right directional dependency control circuit 85. When the instruction is in VLIW mode, the control unit 85 makes division output ineffective. When left-right directional dependency is found, a division instruction from the decoder 82 is sent to a microinstruction generator 98 which generates parallel microinstructions to be sent from a transmitting circuit 99 to the parallel execution pipelines 13 to 16 through a transmission line 100. Division bits are set in a microinstruction and the data dependency is eliminated.

公开(公告)号：JP2000330789A

公开(公告)日：2000-11-30

申请号：JP2000134667

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  FEL BRUNO ,  DUCOUSSO LAURENT

IPC: G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To effectively transfer a protection value between execution units by providing a protection value transfer circuit which can transfer the protection value from master protection to an execution unit. SOLUTION: Each instruction has a protection indicator. A master protection register file is a protection register file 27 of a data unit 18 and a shadow protection register file is given by a control protection register file 101 of a control unit 12. When a data unit 18 executes a protection transmit instruction, a proper protection value is transferred to an address unit 19 or data memory interface control 50. The transferred protection value is held in an A-IDQ protection queue 113 or ARLQ protection queue 114. As for a storage instruction having a storage address added to SAQ 71 of interface control 50, the protection value is transferred from a circuit 112 to an SAQ protection queue 115.

公开(公告)号：DE69934875D1

公开(公告)日：2007-03-08

申请号：DE69934875

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  DUCOUSSO LAURENT ,  FEL BRUNO

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer system has a plurality of parallel execution units for executing instructions with assigned guard indicators, one execution unit including a master guard value store and another execution unit having a shadow guard value store, together with guard ownership circuitry to indicate whether the shadow guard value store owns the current value of the guard indicator and transfer circuitry operable to transfer a guard value from the master store to another execution unit.

公开(公告)号：FR3017226B1

公开(公告)日：2016-01-29

申请号：FR1400289

申请日：2014-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： FEL BRUNO

IPC: G06F21/12

Abstract: Toute portion d'un code programme destinée à être copiée dans la mémoire cache (120) d'un microprocesseur (1) transite chiffrée entre la mémoire vive (6) et le processeur (1) et le déchiffrement est effectué au niveau de la mémoire cache (120). Une somme de contrôle peut être insérée dans les lignes de cache pour permettre une vérification d'intégrité et cette somme de contrôle est alors remplacée par une instruction spécifique avant délivrance d'un mot d'instruction à l'unité centrale (11) du microprocesseur (1).

公开(公告)号：FR3017226A1

公开(公告)日：2015-08-07

申请号：FR1400289

申请日：2014-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： FEL BRUNO

IPC: G06F21/12

Abstract: Toute portion d'un code programme destinée à être copiée dans la mémoire cache (120) d'un microprocesseur (1) transite chiffrée entre la mémoire vive (6) et le processeur (1) et le déchiffrement est effectué au niveau de la mémoire cache (120). Une somme de contrôle peut être insérée dans les lignes de cache pour permettre une vérification d'intégrité et cette somme de contrôle est alors remplacée par une instruction spécifique avant délivrance d'un mot d'instruction à l'unité centrale (11) du microprocesseur (1).

公开(公告)号：DE69938621D1

公开(公告)日：2008-06-12

申请号：DE69938621

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  DUCOUSSO LAURENT ,  FEL BRUNO

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency checks between instructions supplied in the same machine cycle being effective in superscalar mode but disabled in very long instruction word mode.