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公开(公告)号：JP2000330788A
公开(公告)日：2000-11-30
申请号：JP2000135141
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , BOUVIER STEPHANE
Abstract: PROBLEM TO BE SOLVED: To decrease disadvantages in case of a failure in branching by previously holding a usable instruction to be executed by detecting a branch instruction and setting a branch shadow mode, and supplying the instruction continuously. SOLUTION: A program counter 80 is equipped with a takeout branch address unit 218 which holds a target address for branching. A general unit 21 transfers the target address to the takeout branch address unit 218 of a control unit 12 through a bus 23. Branch with a dummy guard is detected by a decoder 82 and the branch shadow mode is set. The branch shadow mode indicates that the setting is reset with a signal on a line 224 from the general unit 21 to the decoder and branching is determined. The branch shadow circuit constitution of the decoder 82 continues to supply instructions after the branch instruction with the dummy guard through a computer and the execution of all allowed following instructions is carried on.
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公开(公告)号：JP2000347854A
公开(公告)日：2000-12-15
申请号：JP2000135053
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , WOJCIESZAK LAURENT , BOUVIER STEPHANE
Abstract: PROBLEM TO BE SOLVED: To provide a decoding device which is simple and good in power efficiency and supplies a decoding output to an execution device accurately according to an instruction mode of a computer. SOLUTION: The decoding device 20 is equipped with 1st and 2nd decoders 50 and 52, and 54 and 56 which are so connected as to receive bit arrays of 1st and 2nd specific lengths. The 1st and 2nd decoders operate in parallel so as to generate respective outputs. Switches MUX6 and MUX7 select one of the outputs according to an instruction mode of a processor. The instruction mode of this processor affects the length of the bit array which needs to actually be decoded.
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公开(公告)号：JP2000330787A
公开(公告)日：2000-11-30
申请号：JP2000135045
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , COFLER ANDREW
Abstract: PROBLEM TO BE SOLVED: To prevent electric power and a load from being applied on a memory access bus by locking a prefetch buffer for further access to a program memory when all loop instructions are present in the prefetch buffer. SOLUTION: A matching part 20 inspects a loop start address by a compactor 77 as to the address of a matching program counter 36. When the same loop start address match is stored in a special buffer 75, this means that a loop is completely included in the prefetch buffer 22. In this case, a lock signal is sent to the prefetch buffer 22. All loop instructions are held in the prefetch buffer 22 with a frequency where the loop instructions need to be executed. Therefore, the lock signal eliminates the need to take the loop instructions out of a program memory repeatedly until the loop is repeated with the prescribed frequency.
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公开(公告)号：JP2000353091A
公开(公告)日：2000-12-19
申请号：JP2000134612
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , FEL BRUNO , DUCOUSSO LAURENT
Abstract: PROBLEM TO BE SOLVED: To provide a computer system in which both a superscaler mode and a VLIW mode are dealt with by instruction scheduling and data dependency between different instruction scan can be processed. SOLUTION: An instruction in a computer system is executed by plural parallel execution pipelines 13 to 16, checks 39 and 42 of dependency in the same row direction are supplied to the parallel pipelines 13 to 16, are executed between other instructions and, moreover, in response to the dependency in the same row direction to be detected, a control signal of a first or a second type is generated by depending upon whether or not the dependency can be released or not by activating a bypass or whether or not a temporary section is obtained for one of the pipelines.
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公开(公告)号：JP2000330790A
公开(公告)日：2000-11-30
申请号：JP2000134618
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , FEL BRUNO , DUCOUSSO LAURENT
Abstract: PROBLEM TO BE SOLVED: To process the data dependency between different instructions by making ineffective a dependency check between instructions in the left-right direction as to instructions of very long instruction word(VLIW) mode. SOLUTION: Instructions are held in a program memory 11, sent to a control unit 12, and supplied to parallel execution pipelines 13 to 16. An instruction is decoded by a decoder 82 and the output of a dependency check circuit 87 is sent to a left-right directional dependency control circuit 85. When the instruction is in VLIW mode, the control unit 85 makes division output ineffective. When left-right directional dependency is found, a division instruction from the decoder 82 is sent to a microinstruction generator 98 which generates parallel microinstructions to be sent from a transmitting circuit 99 to the parallel execution pipelines 13 to 16 through a transmission line 100. Division bits are set in a microinstruction and the data dependency is eliminated.
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Patent Agency Ranking
公开(公告)号：JP2000330789A
公开(公告)日：2000-11-30
申请号：JP2000134667
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , FEL BRUNO , DUCOUSSO LAURENT
Abstract: PROBLEM TO BE SOLVED: To effectively transfer a protection value between execution units by providing a protection value transfer circuit which can transfer the protection value from master protection to an execution unit. SOLUTION: Each instruction has a protection indicator. A master protection register file is a protection register file 27 of a data unit 18 and a shadow protection register file is given by a control protection register file 101 of a control unit 12. When a data unit 18 executes a protection transmit instruction, a proper protection value is transferred to an address unit 19 or data memory interface control 50. The transferred protection value is held in an A-IDQ protection queue 113 or ARLQ protection queue 114. As for a storage instruction having a storage address added to SAQ 71 of interface control 50, the protection value is transferred from a circuit 112 to an SAQ protection queue 115.
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公开(公告)号：GB2366006B
公开(公告)日：2004-06-30
申请号：GB9930587
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , WOJCIESZAK LAURENT , SENAME ISABELLE
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公开(公告)号：GB2362729A
公开(公告)日：2001-11-28
申请号：GB9930588
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , SENAME ISABELLE , BERNARD BRUNO
IPC: G06F9/38
Abstract: A system for executing pipelined instructions, the system including instruction fetch circuitry, instruction dispatch circuitry, data memory for use in store and load operations, data memory access circuitry and emulator circuitry for use in debug operations. The emulator circuitry includes circuitry indicating an error in the data memory access operation, snoop circuitry for snooping memory access in the data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with program counts for the instructions associated with the access addresses and memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
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公开(公告)号：FR2821448B1
公开(公告)日：2004-01-23
申请号：FR0102646
申请日：2001-02-27
Applicant: ST MICROELECTRONICS SA
Inventor： ALOFS THOMAS , COFLER ANDREW
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公开(公告)号：FR2821448A1
公开(公告)日：2002-08-30
申请号：FR0102646
申请日：2001-02-27
Applicant: ST MICROELECTRONICS SA
Inventor： ALOFS THOMAS , COFLER ANDREW
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