公开(公告)号：JPH11354640A

公开(公告)日：1999-12-24

申请号：JP13525599

申请日：1999-05-17

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  GRANGER ERIC

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To control electrical resistance between a wiring and a via of an integrated circuit. SOLUTION: A first dielectric layer 10 and a second dielectric layer 11, which can be selectively etched to the first dielectric layer 10, are deposited on an n-level wiring layer. A hole 13 is formed by etching the first and second dielectric layers and is charged with metal, and via 14 is formed. A third dielectric layer 15 is deposited on the second dielectric layer 11 and the via. The third dielectric layer 15 and the second dielectric layer 11 are etched for forming trenches 18, 19, and etching is stopped on the first dielectric layer 10. The trenches 18, 19 are charged with metal and n-th level and (n+1)-th level wirings are electrically connected by the via 14. Even when there is an offset between via 14 and a wire 20, it is possible to know the height of a side surface part 20a which is in electrical contact therewith and to control the electrical resistance.

公开(公告)号：FR2779274A1

公开(公告)日：1999-12-03

申请号：FR9806687

申请日：1998-05-27

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  GRANGER ERIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

Abstract: Precision selective etching is carried out such that when an offset channel (20) is produced, it extends to a stop zone, and the channel metallization touches the side as well as the base portion of the lower via.

公开(公告)号：FR2779274B1

公开(公告)日：2000-08-18

申请号：FR9806687

申请日：1998-05-27

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  GRANGER ERIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

Abstract: Precision selective etching is carried out such that when an offset channel (20) is produced, it extends to a stop zone, and the channel metallization touches the side as well as the base portion of the lower via.