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    INTEGRATED CIRCUIT AND TEST STRUCTURE
    1.
    发明专利
    INTEGRATED CIRCUIT AND TEST STRUCTURE 失效

    公开(公告)号：JPH11251315A

    公开(公告)日：1999-09-17

    申请号：JP36911598

    申请日：1998-12-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE ,  BRUNEL CHANTAL ,  MARTIN STEPHANE

    IPC: H01L21/3205 ,  G01R31/28 ,  G03F7/20 ,  H01L23/52 ,  H01L23/528

    Abstract: PROBLEM TO BE SOLVED: To judge resistance of a via, by a method wherein, in a position alignment between a path of a metallization layer and the corresponding via, or between the via and the corresponding path, a contact area between the path and the via is corrected with respect to a normal contact area. SOLUTION: First and second path parts 21, 22 are extended to a direction for corresponding vias 24, 25 and come close to all path parts neighboring the via on the same metallization layer from a common side. A continuous part 23 is not placed so that it comes nearer to one of the vias 24, 25 with substantially larger than a width of the via. A contact area is equal irrespective of a direction and an orientation of offsets between a path 20 and the vias 24, 25. All resistances in a part of the predetermined number of vias and paths are calculated, and a value of one via resistance can be obtained, and it is possible to uniformize more the respective via resistances in the entire integrated circuit and to judge an individual via resistance.

    PROCESS FOR MANUFACTURING INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
    2.
    发明专利
    PROCESS FOR MANUFACTURING INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11354640A

    公开(公告)日：1999-12-24

    申请号：JP13525599

    申请日：1999-05-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE ,  GRANGER ERIC

    IPC: H01L21/768 ,  H01L23/522

    Abstract: PROBLEM TO BE SOLVED: To control electrical resistance between a wiring and a via of an integrated circuit. SOLUTION: A first dielectric layer 10 and a second dielectric layer 11, which can be selectively etched to the first dielectric layer 10, are deposited on an n-level wiring layer. A hole 13 is formed by etching the first and second dielectric layers and is charged with metal, and via 14 is formed. A third dielectric layer 15 is deposited on the second dielectric layer 11 and the via. The third dielectric layer 15 and the second dielectric layer 11 are etched for forming trenches 18, 19, and etching is stopped on the first dielectric layer 10. The trenches 18, 19 are charged with metal and n-th level and (n+1)-th level wirings are electrically connected by the via 14. Even when there is an offset between via 14 and a wire 20, it is possible to know the height of a side surface part 20a which is in electrical contact therewith and to control the electrical resistance.

    MANUFACTURE OF METAL INTERCONNECTION IN INTEGRATED CIRCUIT
    3.
    发明专利
    MANUFACTURE OF METAL INTERCONNECTION IN INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11238797A

    公开(公告)日：1999-08-31

    申请号：JP34933598

    申请日：1998-11-25

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： GAYET PHILIPPE

    IPC: H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To obtain structure including the level of a conductor being separated by insulation layers that locally cross by a via being filled with metal, by including a stage for performing retching to the level of a surface at the upper side of a sacrifice layer by chemico-mechanical polishing after depositing metallization. SOLUTION: In a method for manufacturing metallization, the thickness of a dielectric layer 38 where the dielectric layer 38 that is made of a material that cannot be etched easily by a prescribed method, is formed on a support is satisfied based on a predetermined pattern. A sacrificial layer 32 with a desired thickness in a material layer is formed on a support 31, an opening 34 is formed at the sacrificial layer 32 based on a determined pattern, and metallization 35 is formed in the opening 34. Then, the sacrificial layer 32 is eliminated, and the layer of a material 37 which at least exceeding a thickness that is equal to that of a metal pattern is deposited, thus applying to a dielectric material that cannot be etched locally to an edge having a sharp slope.

    6.
    发明专利
    未知

    公开(公告)号：FR2787240A1

    公开(公告)日：2000-06-16

    申请号：FR9815769

    申请日：1998-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE ,  GAYET PHILIPPE

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/8239

    Abstract: Four transistors is formed in a semiconductor substrate and interconnected by a local interconnection layer (M0) situated under a first metallisation level (M1). Two resistances (LIL1,LIL2) provides local interconnection layer between the metallisation layer (M0) and the first metallisation level (M1). An Independent claim is included for: (a) a method of formation of integrated circuit disposed on two levels of metallisation

    8.
    发明专利
    未知

    公开(公告)号：FR2786609B1

    公开(公告)日：2003-10-17

    申请号：FR9814908

    申请日：1998-11-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE

    IPC: H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L23/528 ,  H01L21/3213

    Abstract: The integrated circuit has tracks of at least one metallization layer provided with dielectric layers and metallized vias connecting the tracks of two neighboring layers. At least a part of at least one metallization layer n is divided up into two partial layers offset in height. At least one via (12) connects the track of an upper partial layer and an element located under the dielectric layer of layer n. The via (12) passes through the dielectric layer of the level n and the dielectric material separating the tracks of the lower partial layer. At least one via (13) connects a track of the lower partial layer and a track of a metallization layer n+1. The via (13) passes through the dielectric layer of level n+1 and the dielectric material separating the tracks of the upper partial layer. At least one via connects a track of the lower partial layer and an element located below the dielectric material of level n. The tracks of the part of the metallization layer are distributed between a partial upper level n2 and a partial; lower level n1, and they do not cross each other. The upper and lower partial layers are adjacent and are separated by a supplementary dielectric material layer. An Independent claim is given for a method of manufacturing the integrated circuit.

    9.
    发明专利
    未知

    公开(公告)号：DE69611632T2

    公开(公告)日：2001-08-16

    申请号：DE69611632

    申请日：1996-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE

    IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762

    Abstract: The invention provides a method for producing an isolation region on a surface of a semiconductor substrate comprising the steps of: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and partially removing the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate.

    10.
    发明专利
    未知

    公开(公告)号：FR2803092A1

    公开(公告)日：2001-06-29

    申请号：FR9916488

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

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