公开(公告)号：DE69508659D1

公开(公告)日：1999-05-06

申请号：DE69508659

申请日：1995-06-21

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO-OLIVIER PHILIPPE ,  MAJOUX BERNARD

IPC: G05F3/26 ,  H03K17/041 ,  H03K17/687

Abstract: The voltage source (1) has two parallel transistor paths with two bipolar transistors (T1,T2) forming a mirror pair. A logic circuit provides a logic signal (Standby) to a Standby circuit (2). The standby circuit has an FET transistor, and the logic signal is applied to the gate. The FET source is applied to the voltage supply. The drain is applied to one side of the voltage supply image circuit, disturbing the equilibrium and preventing current flow when switching occurs.

公开(公告)号：DE69508659T2

公开(公告)日：1999-10-07

申请号：DE69508659

申请日：1995-06-21

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO-OLIVIER PHILIPPE ,  MAJOUX BERNARD

IPC: G05F3/26 ,  H03K17/041 ,  H03K17/687

Abstract: The voltage source (1) has two parallel transistor paths with two bipolar transistors (T1,T2) forming a mirror pair. A logic circuit provides a logic signal (Standby) to a Standby circuit (2). The standby circuit has an FET transistor, and the logic signal is applied to the gate. The FET source is applied to the voltage supply. The drain is applied to one side of the voltage supply image circuit, disturbing the equilibrium and preventing current flow when switching occurs.