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12 records (took 0.022 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE60034292D1

    公开(公告)日：2007-05-24

    申请号：DE60034292

    申请日：2000-11-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： SIRITO-OLIVIER PHILIPPE

    IPC: H03L7/08 ,  H03L7/089

    Abstract: The loop has a phase comparator (3) providing logic signal to control the charge pump (16), and a charge feedback circuit (31) also receiving a comparator input to provide a logic signal to the pump. The circuit includes a detector (30) for identifying a current threshold value, which is representative of the current delivered by the pump. The detector output is applied to the feedback circuit, in a manner limiting the duration of the feedback charge.

    2.
    发明专利
    未知

    公开(公告)号：DE69813067D1

    公开(公告)日：2003-05-15

    申请号：DE69813067

    申请日：1998-01-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： SIRITO-OLIVIER PHILIPPE

    IPC: H03B5/36

    Abstract: The circuit includes a voltage controlled quartz oscillator, comprising an oscillation transistor (To) with its base connected to the first terminal of a quartz crystal (1). The emitter of the transistor is connected, via a first capacitor (Ce), to the second terminal of the quartz crystal, which is connected to a first supply terminal (M). The circuit further comprises an active circuit (11) introducing a variable capacitance between the base and the emitter of the oscillation transistor. The active circuit is voltage controlled. The circuit may be extended by the addition of a second capacitor (Cbe) connected between the base and the emitter of the oscillation transistor (To). The active circuit (11) has a structure with differential control receiving a modulating signal.

    4.
    发明专利
    未知

    公开(公告)号：DE602005007857D1

    公开(公告)日：2008-08-14

    申请号：DE602005007857

    申请日：2005-04-14

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： CHIRICOSTA MARIO ,  SIRITO-OLIVIER PHILIPPE

    IPC: H03G1/00

    Abstract: A variable-gain amplifier includes an amplifier stage (17); an attenuating network (14a, 14b) receiving an input signal (V I ) ; a plurality of transconductance stages (15), connected between respective nodes (14a1, 14a2, ..., 14aN, 14b1, 14b2, ..., 14bN) of the attenuating network (14a, 14b) and the amplifier stage (17), wherein each of the transconductance stages (15) has a differential circuit (20), configured to supply differential currents (I D1 , I D2 ) to the amplifier stage (17); and a gain-control circuit (16) for controlling the transconductance stages (15) according to an electrical control quantity (V c ). Each of the transconductance stages (15) further includes a current-divider circuit (21) associated to the differential circuit (20) and controlled by the gain-control circuit (16) so as to divide the differential currents (I D1 , I D2 ) between the amplifier stage (17) and a dispersion line (33) proportionally to the control quantity (V C ).

    SCHUTZ VOR ELEKTROSTATISCHER ENTLADUNG (ESD) FÜR EINE HIGH-SIDE-TREIBERSCHALTUNG
    5.
    发明专利
    SCHUTZ VOR ELEKTROSTATISCHER ENTLADUNG (ESD) FÜR EINE HIGH-SIDE-TREIBERSCHALTUNG 未知

    公开(公告)号：DE102018112509B4

    公开(公告)日：2021-07-22

    申请号：DE102018112509

    申请日：2018-05-24

    Applicant: ST MICROELECTRONICS ALPS SAS ,  ST MICROELECTRONICS SA

    Inventor： MAZOYER YVES ,  GALY PHILIPPE ,  SIRITO-OLIVIER PHILIPPE

    IPC: H01L23/60 ,  H02H9/04 ,  H03K17/08 ,  H03K17/687

    Abstract: Schaltung (100), die Folgendes umfasst:ein Leistungs-MOSFET-Bauteil (102), das eine Gate-Klemme, eine Source-Klemme und eine Drain-Klemme hat;ein Erfassungs-MOSFET-Bauteil (110), das eine Gate-Klemme, eine Source-Klemme und eine Drain-Klemme hat;einen Widerstand (132), der eine erste Klemme hat, die mit der Gate-Klemme des Leistungs-MOSFET-Bauteils (102) gekoppelt ist,-und eine zweite Klemme, die mit der Gate-Klemme des Erfassungs-MOSFET-Bauteils (110) gekoppelt ist;eine Zenerdiode (134), die eine Anodenklemme hat, die mit der Source-Klemme des Erfassungs-MOSFET-Bauteils (110) gekoppelt ist, und eine Kathodenklemme, die mit der Gate-Klemme des Erfassungs-MOSFET-Bauteils (110) gekoppelt ist, undeine Begrenzungsdiode (136), die eine Anodenklemme hat, die mit der Source-Klemme des Erfassungs-MOSFET-Bauteils (110) gekoppelt ist, und eine Kathodenklemme, die mit der Gate-Klemme des Leistungs-MOSFET-Bauteils (102) gekoppelt ist,wobei eine Durchbruchspannung der Zenerdiode (134) kleiner ist als eine Begrenzungsspannung der Begrenzungsdiode.

    9.
    发明专利
    未知

    公开(公告)号：DE69508659D1

    公开(公告)日：1999-05-06

    申请号：DE69508659

    申请日：1995-06-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： SIRITO-OLIVIER PHILIPPE ,  MAJOUX BERNARD

    IPC: G05F3/26 ,  H03K17/041 ,  H03K17/687

    Abstract: The voltage source (1) has two parallel transistor paths with two bipolar transistors (T1,T2) forming a mirror pair. A logic circuit provides a logic signal (Standby) to a Standby circuit (2). The standby circuit has an FET transistor, and the logic signal is applied to the gate. The FET source is applied to the voltage supply. The drain is applied to one side of the voltage supply image circuit, disturbing the equilibrium and preventing current flow when switching occurs.

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