公开(公告)号：JPH11225334A

公开(公告)日：1999-08-17

申请号：JP32157498

申请日：1998-11-12

Applicant: ST MICROELECTRONICS SRL

Inventor： PAU DANILO ,  ROVATI FABRIZIO ,  VALSASNA ANNA ,  BRUNI ROBERTA

IPC: H04N5/93 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To obtain a device which calculates the dispersion value of a macroblock of a digital video by outputting the square value of an image that is continuously inputted, inputting each pixel of the macroblock, counting up, resetting a counter simultaneously with the input of a final pixel, transmitting the pixel value and square value of a pixel to an accumulator and storing accumulative result value of the accumulator. SOLUTION: For an algorithm that is executed by an accelerator for dispersion value calculation, a simple counter LC is used and two demultiplexers transmit an input line which processes in a method such as decides to which dispersion value a prescribed input pixel belongs to eight separate dispersion value operation paths. Relating to a prescribed line pattern in which a macroblock is scanned, as a rule, the bit of the counter LC that drives multiplexers is selected so that a dispersion value can be accurately operated. The counter LC is reset at the time of starting each macroblock and is counted up by the input of each pixel.

公开(公告)号：JP2003208306A

公开(公告)日：2003-07-25

申请号：JP2002347918

申请日：2002-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CREMONESI ALESSANDRO ,  ROVATI FABRIZIO ,  PAU DANILO

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To provide a processing architecture capable of executing two or more different sets of instructions. SOLUTION: The architecture comprises a single CPU configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2,...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3,...). The single CPU is configured for being switched between a first operating mode, in which the single CPU executes the first set instructions (OsTask1.1, OsTask1.2,...) and a second operating mode, in which the single CPU executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3,...). The solution can be generalized by the use of a plurality of switching instructions between more than two execution modes for different CPUs. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001103521A

公开(公告)日：2001-04-13

申请号：JP2000266755

申请日：2000-09-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PAU DANILO ,  LUCA PEZZONI ,  ROVATI FABRIZIO ,  SIRTORI DANIELE

IPC: H04N7/32 ,  H04N7/26 ,  H04N17/00

Abstract: PROBLEM TO BE SOLVED: To provide a technology that detects whether contents of a picture in a video sequence are of a progressive type or an interlace type. SOLUTION: The technology of this invention demarcates a bottom field Bc of a current picture, a top field Tc of the current picture, a bottom field Bp of a preceding picture, and a top field Tp of the preceding picture. Settling whether the current picture decomposed into the fields Bc and Tc is a progressive picture or an interlace picture recognizes whether contents of the video picture are progressive or interlace contents.

公开(公告)号：DE69937557D1

公开(公告)日：2007-12-27

申请号：DE69937557

申请日：1999-09-03

Applicant: ST MICROELECTRONICS SRL

Inventor： PAU DANILO ,  PEZZONI LUCA ,  ROVATI FABRIZIO ,  SIRTORI DANIELE

IPC: H04N7/26 ,  H04N7/32 ,  H04N7/36 ,  H04N17/00

Abstract: A method of recognizing a progressive or an interlaced content of video pictures during their processing in a coder, comprises the following operations on at least on one of the components (luminance or chrominance) of the video signal: a) defining a macroblock belonging to a frame of the preceding picture having dimensions R*S pixels, a half of it (R/2)*S being placed on the Top field Tp and the other half on the Bottom field Bp; b) for the chosen component of the video signal, calculating a first pair of coefficients (COEFF_1, COEFF_2) equivalent to the sum, extended to all the columns and to all the even row of said macroblock, of the absolute values of the differences among the values assumed by said component of the video signal in the pixels of the same column and of consecutive rows belonging to the Top semi-frame and Bottom semi-frame, respectively, and the sum, extended to all the columns and to each fourth row of said macroblock, of the absolute values of the differences among the values assumed by said component of the video signal in the pixels of the same column and of consecutive rows of the same parity belonging to the Top semi-frame and Bottom semi-frame respectively; c) verifying whether the first one of the coefficients of said pair is greater than or equal to a prefixed first real positive number of times (a) of the second coefficient, incrementing a first counter (CONT_1) at each positive verification; d) incrementing a second counter (NUM_MACROBLOCK) at each macroblock so tested; e) calculating for each row of each Top semi-frame a second pair of coefficients (COEFF_3, COEFF_4) equivalent to for each row the sum, extended to all the columns of each semi-frame of the absolute values of the differences among the values assumed by said component of the video signal in pixels of the Bottom semi-frame of the preceding picture and of the Bottom semi-frame of the current picture, belonging to the row following the considered row and to the same column, and the sum, extended to all the columns of each semi-frame of the absolute values of the differences among the values assumed by said component of the video signal in pixels of the same column and, respectively, of said row of the Top semi-frame of the preceding picture and the row following the considered row, belonging to the Bottom semi-frame of the current picture, respectively; f) verifying whether the second coefficient of said second pair is grater than or equal to a second prefixed real positive number of times ( beta ) the first coefficient of said second pair, incrementing a third counter (CONT_2) at each positive verification; g) incrementing a fourth counter (NUM_RIGHE) at each row so tested; verifying whether the content of the first counter (CONT_1) is greater than or equal to a third prefixed real positive number of times ( gamma ) the content of second counter (NUM_MACROBLOCK) and whether, at the same time, the content of the third counter (CONT 2) is greater than or equal to a fourth prefixed real positive number of times ( delta ) the content of the fourth counter (NUM_RIGHE): if so, considerating the frame composed of said Top and Bottom semi-frame an interlaced one, if not a progressive one.

公开(公告)号：DE60215318D1

公开(公告)日：2006-11-23

申请号：DE60215318

申请日：2002-06-07

Applicant: ST MICROELECTRONICS SRL

Inventor： ALFONSO DANIELE ,  ROVATI FABRIZIO

IPC: H04N7/26

Abstract: A system for generating motion vectors (MV) in the framework of a motion estimator is configured for co-operating with an engine for calculating estimation error for generating motion vectors (MV), according to estimation errors and/or motion vectors previously generated. The system comprises a program memory (40), which is able to contain program data for a motion-estimation algorithm to be executed, as well as a motion-vector memory (42), which is able to contain data identifying said motion vectors previously calculated. The system further comprises an arithmetic and logic unit (46) co-operating with the aforesaid program memory (40) and motion-vector memory (42), with the possibility of generating motion vectors (MV) in a programmable way so as to get them to correspond, for example, to predictors deriving from motion-estimation operations already performed on the macroblocks of the reference frame or on the previous macroblocks of the current frame, as updates calculated using the coordinates of the motion vectors already issued for the current macroblock, or again as absolute motion vectors, generated as such, taking the components directly from the program code.