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1.发明专利
公开(公告)号：JP2003208306A
公开(公告)日：2003-07-25
申请号：JP2002347918
申请日：2002-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： CREMONESI ALESSANDRO , ROVATI FABRIZIO , PAU DANILO
Abstract: PROBLEM TO BE SOLVED: To provide a processing architecture capable of executing two or more different sets of instructions. SOLUTION: The architecture comprises a single CPU configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2,...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3,...). The single CPU is configured for being switched between a first operating mode, in which the single CPU executes the first set instructions (OsTask1.1, OsTask1.2,...) and a second operating mode, in which the single CPU executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3,...). The solution can be generalized by the use of a plurality of switching instructions between more than two execution modes for different CPUs. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JPH0846487A
公开(公告)日：1996-02-16
申请号：JP16657095
申请日：1995-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLE FESTE SANDRO , BIANCHESI MARCO , CREMONESI ALESSANDRO
Abstract: PURPOSE: To satisfy timewise limitation conditions to filter components with a filter having serial architecture with a finite impulse response(FIR) while having a simple controller. CONSTITUTION: This oversampling digital filter is composed of a memory means M1 for coefficients, memory means M2 for sampling signals to be filtered, multiplier MU connected to the output terminals of memory means M1 and M2, accumulator AC connected to the output terminal of that multiplier MU, and simple controller CU for controlling elements based on a clock signal CLK received at the input terminal of that accumulator.
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公开(公告)号：JPH06350399A
公开(公告)日：1994-12-22
申请号：JP865394
申请日：1994-01-28
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: PURPOSE: To enable the high resolution processing of a digital sampling signal by sampling an input signal based on different filtering mode or operation and adding a digital output from each filtering operation so as to reconstitute an output signal. CONSTITUTION: A 7-bit input signal S1 is impressed to the input terminal of a filter 2, which outputs a 16-bit signal S2 of address-designating the input side of a switch 3. The signal S2 directly fetched from the filter 2 alternately expresses conversion executed by the filtering section of the different transmitting function of the filter 2. The switch 3 is assigned with a task address- designating the signal S3 to an adder circuit 5 and a delay circuit 4. The circuit 4 introduces a delay time equal to a time required for the filter 2 to process a signal. Consequently, the circuit 5 adds the output of the two filtering section of the filter 2 to reconstitute a final signal.
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公开(公告)号：JPH06350398A
公开(公告)日：1994-12-22
申请号：JP780794
申请日：1994-01-27
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: PURPOSE: To enable the high resolution processing of a coded digital sampling signal by dividing an inputted sampling signal into at least two parts and filtering each part without regard to the other parts by the digital filter of each to reconstitute an output sampling signal. CONSTITUTION: A digital signal S with a 9-bit code is impressed to a decoder D to select eight highest order digit bits to output a signal S1 to a first programmable digital filter (PFP) 2 and an adder 4. The adder 4 receives a pit a0 with the maximum weight of the lowest order digit part of the digital signal S selected by the decoder D at the other input terminal and generates an 8-bit signal S2 to input as an address signal to the address terminal of second PFP 2. Output from two PFP 2 are added by an adder 5 to correctly reconstitute an output signal. Consequently a signal with a high dynamic range is given high resolution processing.
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Patent Agency Ranking
公开(公告)号：DE69428526D1
公开(公告)日：2001-11-08
申请号：DE69428526
申请日：1994-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLE FESTE SANDRO , BIANCHESI MARCO , CREMONESI ALESSANDRO
Abstract: The oversampling digital filter with Finite Impulse Response is implemented by means of a serial structure comprising a memory means (M1) for the coefficients, a memory means (M2) for the signal samples to be filtered, a multiplier (MU) connected to the output of said memories (M1, M2), an accumulator (AC) connected to the output of the multiplier (MU), and a simple control unit (CU) which controls said elements on the basis of a clock signal (CLK) which it receives at input.
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公开(公告)号：DE69324789T2
公开(公告)日：1999-09-16
申请号：DE69324789
申请日：1993-01-29
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
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公开(公告)号：DE69324789D1
公开(公告)日：1999-06-10
申请号：DE69324789
申请日：1993-01-29
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
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公开(公告)号：DE69316186T2
公开(公告)日：1998-04-16
申请号：DE69316186
申请日：1993-01-29
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: A method of filtering digital signals having a high dynamic range comprises the steps of: splitting the sampled input signal (S) into at least two portions; addressing each of said portions (S1,S2,...,Sm) to a respective program filter (2), and performing each filtering operation in parallel and independently; and reconstituting an output signal by summing together the digital outputs from each filter (2).
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公开(公告)号：DE69316186D1
公开(公告)日：1998-02-12
申请号：DE69316186
申请日：1993-01-29
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: A method of filtering digital signals having a high dynamic range comprises the steps of: splitting the sampled input signal (S) into at least two portions; addressing each of said portions (S1,S2,...,Sm) to a respective program filter (2), and performing each filtering operation in parallel and independently; and reconstituting an output signal by summing together the digital outputs from each filter (2).
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