公开(公告)号：EP2423950B1

公开(公告)日：2020-04-15

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics, Inc.

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01C1/148 ,  H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L21/768 ,  H01C7/00

公开(公告)号：EP2423950A3

公开(公告)日：2013-05-01

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics, Inc.

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L21/768 ,  H01C7/00

Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

公开(公告)号：EP2423950A2

公开(公告)日：2012-02-29

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Inc

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

Abstract translation: 本发明涉及的薄膜电阻器结构（100）包括一电阻性元件那样（102），其电连接第一导体层（106A，B）相邻的互连结构（104A，B）。 所述电阻元件由介电覆盖层覆盖（105）确实用作稳定剂和散热器为电阻元件。 每个互连件包括在所述第一导电层的第二导体层（124）。 薄膜电阻器包括由硅氮化物帽层覆盖的硅铬电阻元件。

公开(公告)号：EP1840959A1

公开(公告)日：2007-10-03

申请号：EP07251306.2

申请日：2007-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Niu, Chengyu

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76865

Abstract: A hybrid ionized physical vapor deposition technique to form liner films for vias, trenches, and other structures of integrated circuits. The techniques involves depositing liner materials within a via, hole, trench, or other structure in a neutral state, using, for example, physical vapor deposition. The liner materials deposited in this step have an ionization ratio of less than ten percent, and no bias potential is applied to an underlying substrate. The technique also involves depositing liner materials in ionized form in the same via using ionized physical vapor deposition. The liner materials deposited in this step have an ionization ratio far more than ten percent, and an optional bias potential may be applied to the underlying substrate. After liner film is formed, any other suitable actions or processing steps may take place including building additional metallization and dielectric layers and vias or trenches to produce a multi-level interconnect system.

Abstract translation: 用于形成用于通孔，沟槽和集成电路的其他结构的衬垫膜的混合电离物理气相沉积技术。 这些技术涉及使用例如物理气相沉积在中性状态的通孔，孔，沟槽或其它结构中沉积衬垫材料。 在该步骤中沉积的衬垫材料具有小于10％的电离比，并且没有偏压电位施加到下面的衬底。 该技术还涉及使用电离物理气相沉积在相同的通孔中沉积离子化形式的衬垫材料。 在该步骤中沉积的衬垫材料的电离比率远高于百分之十，并且可以将偏置电位施加到下面的衬底上。 在形成衬里膜之后，可以发生任何其它合适的动作或处理步骤，包括建立附加的金属化和介电层以及通孔或沟槽以产生多层互连系统。