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    A device for implementing a sum of products expression
    1.
    发明公开
    A device for implementing a sum of products expression 审中-公开
    Eine Vorrichtung zur Implementierung eines Summenprodukt-Ausdrucks

    公开(公告)号：EP1650869A1

    公开(公告)日：2006-04-26

    申请号：EP05109736.8

    申请日：2005-10-19

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Bhuvanagiri, Aditya ,  Malik, Rakesh ,  Chawla, Nitin

    IPC: H03H17/02 ,  G06F7/00 ,  G06F17/50

    CPC classification number: H03H17/0225

    Abstract: The present invention provides a device for implementing a sum-of-products expression comprising a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/ complex sum-of -products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from said 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein , a third set of 2SAD blocks receiving recursively and vertically optimized response from said first set of 2SAD block and said second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from said blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from said fourth set of 2SAD blocks, for generating the final output.

    Abstract translation: 本发明提供了一种用于实现产品总和表达式的装置，包括：第一组2-输入移位和加法（2SAD）块，其接收用于产生第一组的第一组的系数组/复数和和积表达式 通过在其中应用递归优化来实现部分优化的表达项;第二组1-输入移位和加法（1SAD）块，其从所述2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化表达项，第三组 一组2SAD块从所述第一组2SAD块和所述第二组1SAD块接收递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第四组2SAD块从所述 用于通过应用分解和因式分解来产生第四组部分优化的表达式的块，以及第五组2SAD块 接收来自所述第四组2SAD块的响应，用于产生最终输出。

    Spread spectrum clock generation system
    4.
    发明公开
    Spread spectrum clock generation system 有权
    Tak g ators er er er er。。。

    公开(公告)号：EP1858157A1

    公开(公告)日：2007-11-21

    申请号：EP07108245.7

    申请日：2007-05-15

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Chawla, Nitin

    IPC: H03C3/09 ,  H04B1/69 ,  H03B29/00 ,  H03L7/197

    CPC classification number: H04B1/69 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/1976 ,  H03M7/3026 ,  H03M7/3042

    Abstract: The present invention provides a spread spectrum clock generation system, comprising a digitally controlled Phase Locked Loop (PLL), and a Digital Frequency Profile Generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required Noise Transfer Function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band Signal-to-Noise-Ratio (SNR) at the cost of higher out-of-band noise.

    Abstract translation: 本发明提供一种包括数字控制的锁相环（PLL）和数字频率分布生成器的扩展频谱时钟生成系统，用于为了实现输出频率调制时钟中的频谱平坦度而创建近似最佳频率调制曲线。 该电路与多电平误差反馈噪声整形结构相结合，为结构量化噪声提供所需的噪声传递函数，但保持单位增益全通信号传递功能。 这种布置以较高的带外噪声为代价，可以降低带内信噪比（SNR）。

    A minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry
    5.
    发明公开
    A minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权
    一个Polyphaseninterpolationsfilters的使用所述系数对称性以集成电路的最小空间要求执行

    公开(公告)号：EP1630958A3

    公开(公告)日：2007-03-07

    申请号：EP05018679.0

    申请日：2005-08-29

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Bhuvanagiri, Aditha ,  Singh, Halvinder ,  Malik, Rakesh ,  Chawla, Nitin

    IPC: H03H17/06 ,  H03H17/02

    CPC classification number: H03H17/0275 ,  H03H17/0657

    Abstract: A minimal area integrated circuit implementation of a polyphase interpolation filter using symmetry of coefficients for at least one channel of input data, comprising, an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a channel select multiplexer block selecting a channel in response to a first set of internal control signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals , an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block for synchronization of filtered signal, and a control block to generate clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware requirement of coefficient set implementation in a polyphase interpolation filter.

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