公开(公告)号：EP0902465B1

公开(公告)日：2008-10-15

申请号：EP97830427.7

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cassio, Valerio ,  Caprara, Paolo ,  Cereda, Manlio Sergio

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

公开(公告)号：EP0902465A1

公开(公告)日：1999-03-17

申请号：EP97830427.7

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cassio, Valerio ,  Caprara, Paolo ,  Cereda, Manlio Sergio

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors.
The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.

Abstract translation: 本发明涉及一种用于制造集成在半导体上并包括浮动栅极存储单元的矩阵（3）的电子虚拟接地存储器件的方法，该矩阵形成在具有多个连续位线（7）的半导体衬底上 ）作为离散的平行条纹延伸穿过基底（10）。 该矩阵包括用于选择晶体管（20）的电路部分（C'），以及包括具有P沟道和N沟道MOS晶体管的解码和寻址电路部分（A，B）的存储器件。 本发明的方法至少包括以下步骤：在至少一个（A）所述衬底部分中形成N阱（11）以容纳所述P沟道晶体管，借助于屏蔽掩模限定所有晶体管的有效面积 （33），然后通过所述掩模（33）的孔生长隔离层（13）。 有源区域定义掩模（33）在存储器单元的矩阵区域（C“）上不开放。

公开(公告)号：EP0902466A1

公开(公告)日：1999-03-17

申请号：EP97830428.5

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cassio, Valerio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of manufacturing a P-channel native MOS transistor (7) in a circuit integrated on a semiconductor (1) which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels (5,10) having an interpoly dielectric layer sandwiched between the two polysilicon levels, comprises the following steps:

masking and defining active areas (2) of the discrete integrated devices;
masking and defining the first polysilicon level (5) using a Poly1 mask; and
masking and defining an intermediate dielectric layer (8) using a Matrix mask (9).

The length of the native threshold channel of the native transistor is defined by means of the Matrix mask (9) and by etching away the interpoly dielectric layer (8). A subsequent step of masking and defining the second polysilicon level (10) provides for the use of a Poly2 mask (12) which extends the active area of the transistor (7) with a greater width than the previous mask (9) in order to enable, by subsequent etching, the two polysilicon levels (5,10) to overlap in self-alignment over the channel region.

Abstract translation: 一种在集成在半导体（1）上的电路中制造P沟道天然MOS晶体管（7）的方法，该半导体还包括具有两个多晶硅层（5,10）的浮置型的非易失性存储单元的矩阵， 夹在两个多晶硅层之间的多晶硅介电层包括以下步骤：屏蔽和限定离散集成器件的有源区域（2）; 使用Poly1掩模掩蔽和限定第一多晶硅层（5）; 以及使用矩阵掩模（9）掩蔽和限定中间介电层（8）。 通过矩阵掩模（9）和蚀刻掉多晶硅介电层（8）来限定天然晶体管的天然阈值通道的长度。 掩蔽和限定第二多晶硅层（10）的后续步骤提供使用Poly2掩模（12），其以比先前的掩模（9）更大的宽度延伸晶体管（7）的有源区域，以便 通过随后的蚀刻使得两个多晶硅层（5,10）能够在沟道区域上自对准重叠。

公开(公告)号：EP0902466B1

公开(公告)日：2005-01-19

申请号：EP97830428.5

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cassio, Valerio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

公开(公告)号：EP0902463A1

公开(公告)日：1999-03-17

申请号：EP97830433.5

申请日：1997-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Cassio, Valerio ,  Wurthwein, Arturo

IPC: H01L21/321 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/32139

Abstract: A method of manufacturing a plurality of floating gate regions lying parallel on a semiconductor substrate (10), and of inhibiting the formation of residue materiallaterally contiguous to each floating gate region, comprises the following steps: growing a thin oxide layer (13) over the semiconductor substrate (10); depositing a first layer (14) of polysilicon to fully cover the first thin oxide layer; growing and/or depositing an intermediate dielectric layer (15) over the first layer (14) of polysilicon; depositing a second layer (16) of polysilicon to fully cover the intermediate dielectric layer (15). This method further comprises the steps of depositing a final dielectric layer (17) to cover the previously deposited and/or grown layers (13,14,15,16); depositing a layer of resist onto the final dielectric layer, followed by a photolithographing step to define a planar geometry bounding the floating gate regions; and carrying out a first etching to only transfer this planar geometry onto the final dielectric layer (17), thereby producing a mask for a late second etching of the self-aligned type; thoroughly removing the layer of resist; carrying out a second self-aligned etching to spatially define the floating gate regions with a vertical profile.

Abstract translation: 制造浮在一个半导体衬底（10）位于平行的栅极区域中的多个方法，和残余材料尾盘反弹邻接的各浮栅区的形成，抑制的方法包括以下步骤：生长在一薄的氧化物层（13） 半导体衬底（10）; 沉积多晶硅完全覆盖第一薄氧化物层的第一层（14）; 生长和/或在多晶硅的第一层（14）中间介电层（15）上沉积; 沉积多晶硅的第二层（16）完全覆盖中间介电层（15）。 该方法还包括沉积最终介电层（17），以覆盖先前沉积和/或生长的层（13,14,15,16）的步骤; 沉积抗蚀剂层到最终的介电层，接着是步骤photolithographing以限定平面的几何形状界定浮栅区; 并进行第一蚀刻，以仅传输该平面的几何形状到最终的介电层（17），由此产生的自对准型的后期第二蚀刻的掩模; 彻底除去抗蚀剂的层; 进行第二自对准蚀刻到空间上与垂直轮廓限定在浮置栅极区域。