公开(公告)号：EP0902463A1

公开(公告)日：1999-03-17

申请号：EP97830433.5

申请日：1997-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Cassio, Valerio ,  Wurthwein, Arturo

IPC: H01L21/321 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/32139

Abstract: A method of manufacturing a plurality of floating gate regions lying parallel on a semiconductor substrate (10), and of inhibiting the formation of residue materiallaterally contiguous to each floating gate region, comprises the following steps: growing a thin oxide layer (13) over the semiconductor substrate (10); depositing a first layer (14) of polysilicon to fully cover the first thin oxide layer; growing and/or depositing an intermediate dielectric layer (15) over the first layer (14) of polysilicon; depositing a second layer (16) of polysilicon to fully cover the intermediate dielectric layer (15). This method further comprises the steps of depositing a final dielectric layer (17) to cover the previously deposited and/or grown layers (13,14,15,16); depositing a layer of resist onto the final dielectric layer, followed by a photolithographing step to define a planar geometry bounding the floating gate regions; and carrying out a first etching to only transfer this planar geometry onto the final dielectric layer (17), thereby producing a mask for a late second etching of the self-aligned type; thoroughly removing the layer of resist; carrying out a second self-aligned etching to spatially define the floating gate regions with a vertical profile.

Abstract translation: 制造浮在一个半导体衬底（10）位于平行的栅极区域中的多个方法，和残余材料尾盘反弹邻接的各浮栅区的形成，抑制的方法包括以下步骤：生长在一薄的氧化物层（13） 半导体衬底（10）; 沉积多晶硅完全覆盖第一薄氧化物层的第一层（14）; 生长和/或在多晶硅的第一层（14）中间介电层（15）上沉积; 沉积多晶硅的第二层（16）完全覆盖中间介电层（15）。 该方法还包括沉积最终介电层（17），以覆盖先前沉积和/或生长的层（13,14,15,16）的步骤; 沉积抗蚀剂层到最终的介电层，接着是步骤photolithographing以限定平面的几何形状界定浮栅区; 并进行第一蚀刻，以仅传输该平面的几何形状到最终的介电层（17），由此产生的自对准型的后期第二蚀刻的掩模; 彻底除去抗蚀剂的层; 进行第二自对准蚀刻到空间上与垂直轮廓限定在浮置栅极区域。

公开(公告)号：EP0893825A1

公开(公告)日：1999-01-27

申请号：EP97830383.2

申请日：1997-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Locati, Vanda ,  Wurthwein, Arturo ,  Villa, Monica ,  Clemente, Gino ,  Lo Priore, Stefano

IPC: H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/76224 ,  H01L21/76819

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), which devices comprise a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, within said trench regions (3), of a dielectric stack structure comprising a first layer (4) of undoped oxide, a second layer (5) of oxide deposited over said first layer (4), and a third layer (6) of capping oxide. Also provided are two planarizing substeps consisting of a chemio-mechanical clearing substep followed by a dry etch-back substep to expose the top surfaces of said gate regions (2).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面度的平面化方法，该器件包括形成有栅极区域（2）的多个有源元件，所述栅极区域（2）以衬底（1）表面为傲，并且限定沟槽区域 ）。 该方法提供在所述沟槽区域（3）内沉积包括未掺杂氧化物的第一层（4），沉积在所述第一层（4）上的氧化物的第二层（5））的介电堆叠结构，以及 第三层（6）覆盖氧化物。 还提供了两个平坦化子步骤，其由化学机械清除子步骤，随后是干蚀刻子步骤，以暴露所述栅极区域（2）的顶表面。