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    Method for autoaligning overlapped lines of conductor material provided in integrated electronic circuits
    1.
    发明公开
    Method for autoaligning overlapped lines of conductor material provided in integrated electronic circuits 有权
    一种用于在集成电子电路重叠导电迹线的自对准方法

    公开(公告)号：EP1058304A1

    公开(公告)日：2000-12-06

    申请号：EP99830336.6

    申请日：1999-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/3011

    Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps:

    forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another;
    forming a fill layer (4) in the gaps between said regions (3) ;
    planarizing said fill layer (4) to expose said regions (3) ;
    removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3);
    forming an insulating layer (6) in said holes (5);
    selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ;
    depositing at least one conductive layer (8) all over the exposed surface;
    photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).

    Abstract translation: 形成，在所述半导体衬底（2），（3）从所述基板突出区域的多元性：用于autoaligning的导电材料线（WL）的集成（2）上，其包括以下步骤的半导体衬底的电路的改进的方法 （2）表面和彼此对齐; 在形成所述区域之间的间隙的填充层（4）（3）; 所述填充平坦化层（4），以露出所述区域（3）; 去除所述的区域的表面部分（3），以形成孔（5），在所述区域的位置（3）; 上形成绝缘层（6）在所述孔（5）; 选择性地去除所述电介质层（6），以形成间隔物（7）沿所述孔的边缘（5）; 沉积至少一层导电层（8）在整个暴露的表面; 用掩模photolithographing并蚀刻掉层（8），以限定线（WL），并将它们准直到底层区域（3）。

    Electrically programmable non-volatile semiconductor memory
    2.
    发明公开
    Electrically programmable non-volatile semiconductor memory 审中-公开
    Elektrisch programmierbarenichtflüchtigeHalbleiterspeicheranordnung

    公开(公告)号：EP0978845A1

    公开(公告)日：2000-02-09

    申请号：EP98830490.3

    申请日：1998-08-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Caprara, Paolo

    IPC: G11C16/04

    CPC classification number: G11C16/30 ,  G11C16/0416

    Abstract: Electrically programmable non-volatile memory device, comprising an array (1) of memory cells (MC) arranged in rows (WL n -WL n+3 ) and columns (BL n -BL n+4 ) with common source diffusions (SD) contacted by at least one conductive matrix source line (SL n ,SL n+1 ) coupled to an external source bias voltage conductor (SELsource) external to the memory cell array carrying a voltage to be applied to source regions of the memory cells in the memory cell array. At least one resistive means (10) is connected in series between the at least one matrix source line and the external source bias voltage conductor, the resistive means being external to the memory cell array and being suitable to cause a rise in a voltage of the source regions of the memory cells when run through by a memory cell programming current during a programming operation of the memory device.

    Abstract translation: 电气可编程非易失性存储器件，包括排列成行（WLn-WLn + 3）的存储器单元阵列（1）和具有共同源扩散（SD）的列（BLn-BLn + 4），至少与 一个导体矩阵源极线（SLn，SLn + 1），其耦合到存储单元阵列外部的外部源偏压电压导体（SELsource），所述外部源极偏置电压导体承载要施加到存储器单元阵列中的存储器单元的源极区域的电压。 至少一个电阻装置（10）串联连接在至少一个矩阵源极线和外部源极偏置电压导体之间，电阻装置在存储单元阵列的外部，并且适于引起电压的上升 在存储器件的编程操作期间通过存储器单元编程电流运行时存储器单元的源极区域。

    Method for manufacturing a native MOS P-channel transistor with a process manufacturing non-volatile memories
    3.
    发明公开
    Method for manufacturing a native MOS P-channel transistor with a process manufacturing non-volatile memories 失效
    Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit VerfahrenfürnichtflüchtigeSpeicher

    公开(公告)号：EP0902466A1

    公开(公告)日：1999-03-17

    申请号：EP97830428.5

    申请日：1997-08-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cassio, Valerio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

    IPC: H01L21/8239 ,  H01L27/105

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

    Abstract: A method of manufacturing a P-channel native MOS transistor (7) in a circuit integrated on a semiconductor (1) which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels (5,10) having an interpoly dielectric layer sandwiched between the two polysilicon levels, comprises the following steps:

    masking and defining active areas (2) of the discrete integrated devices;
    masking and defining the first polysilicon level (5) using a Poly1 mask; and
    masking and defining an intermediate dielectric layer (8) using a Matrix mask (9).

    The length of the native threshold channel of the native transistor is defined by means of the Matrix mask (9) and by etching away the interpoly dielectric layer (8). A subsequent step of masking and defining the second polysilicon level (10) provides for the use of a Poly2 mask (12) which extends the active area of the transistor (7) with a greater width than the previous mask (9) in order to enable, by subsequent etching, the two polysilicon levels (5,10) to overlap in self-alignment over the channel region.

    Abstract translation: 一种在集成在半导体（1）上的电路中制造P沟道天然MOS晶体管（7）的方法，该半导体还包括具有两个多晶硅层（5,10）的浮置型的非易失性存储单元的矩阵， 夹在两个多晶硅层之间的多晶硅介电层包括以下步骤：屏蔽和限定离散集成器件的有源区域（2）; 使用Poly1掩模掩蔽和限定第一多晶硅层（5）; 以及使用矩阵掩模（9）掩蔽和限定中间介电层（8）。 通过矩阵掩模（9）和蚀刻掉多晶硅介电层（8）来限定天然晶体管的天然阈值通道的长度。 掩蔽和限定第二多晶硅层（10）的后续步骤提供使用Poly2掩模（12），其以比先前的掩模（9）更大的宽度延伸晶体管（7）的有源区域，以便 通过随后的蚀刻使得两个多晶硅层（5,10）能够在沟道区域上自对准重叠。

    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell
    5.
    发明公开
    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell 有权
    电子存储装置，包括非易失性存储器单元具有高密度和减小电容的细胞 - 细胞干扰

    公开(公告)号：EP1672645A1

    公开(公告)日：2006-06-21

    申请号：EP05027285.5

    申请日：2005-12-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Caimi, Carlo ,  Mastrodomenico, Giovanni ,  Caprara, Paolo

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    Abstract: Electronic memory device with non-volatile memory cells, high density and reduced interference cell-to-cell, of the type integrated on a semiconductor substrate (3) and organised in matrix with rows or Word lines (4) and columns or Bit lines (5) of memory cells (2). Each of said cells (2) comprises at least one floating gate transistor having a floating gate region (9) projecting from said substrate (3) and a control gate region (12) capacitively coupled to said floating gate region (9). Between the cells (2) of said opposite Word lines (4) a lateral coating (15) is provided comprising at least one conductive layer (16) floating along the direction of said Bit lines (5).

    Abstract translation: 具有非易失性存储器单元，高密度和减小的干扰细胞至细胞，集成在一个半导体衬底（3）和组织在一个矩阵的行或字线（4）和列线或位线（所述类型的电子存储器设备 存储器单元5）（2）。 每个所述电池（2）包括至少一个浮动具有（9），从电容性耦合到所述浮栅区域，在所述基片（3）和控制栅极区域（12）突出的浮栅区栅极晶体管（9）。 将细胞（2）之间的所述相对的字线（4）的横向的涂层（15）设置的至少一个包括用导电层（16）沿所述位线的方向浮动的（5）。

    Process for manufacturing electronic memory devices with cells matrix having virtual ground
    7.
    发明公开
    Process for manufacturing electronic memory devices with cells matrix having virtual ground 有权
    用于电子存储器装置具有单元阵列虚拟地制造工艺

    公开(公告)号：EP1032035A1

    公开(公告)日：2000-08-30

    申请号：EP99830100.6

    申请日：1999-02-26

    Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

    Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

    IPC: H01L21/8247

    CPC classification number: H01L27/11521

    Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

    forming an oxide layer (3) over the matrix region;
    depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6);
    forming a second dielectric layer (7);
    defining floating gate regions (13) by photolithography using a mask of "POLY1 along a first predetermined direction", and associated etching, to define, in said stack structure, a plurality of parallel openings (9);
    implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions;
    filling the parallel openings (12) with a photo-sensitive material (11) to protect the matrix bit lines (10).

    Abstract translation: 一种用于制造具有虚地电子半导体集成电子存储器设备和包括至少浮动栅极存储器单元的一个矩阵处理（1）中，基体被连续位线的延伸的多个（10）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：在所述矩阵区域氧化物层（3）上; 沉积半导体整个具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层（6）; 形成第二电介质层（7）; 使用的“沿第一预定方向POLY1”掩模，和相关联的蚀刻， - 定义浮置栅极区域（13），通过光刻，以限定在所述堆叠结构，平行的开口（9）的多元性; 注入所述平行的开口（9），以赋予对位线（10）的区域的预定导电性; 填充开口（12）在平行（11）光敏材料，以保护基质的位线（10）。

    Process for manufacturing a dual charge storage location memory cell
    10.
    发明公开
    Process for manufacturing a dual charge storage location memory cell 有权
    用于制造双电荷存储位置存储器单元的过程

    公开(公告)号：EP1300888A1

    公开(公告)日：2003-04-09

    申请号：EP01830634.0

    申请日：2001-10-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Caprara, Paolo ,  Brambilla, Claudio ,  Cereda, Manlio Sergio

    IPC: H01L29/792 ,  H01L21/8246 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

    Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell comprises the steps of: forming a central insulated gate ( 12 , 15 ) over a semiconductor substrate ( 11 ); forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack ( 19 , 110 , 111 ; 29 , 210 , 211;49A , B , 410A , B , 411A , B ) at the sides of the central gate, the charge trapping material layer ( 110 ; 210 ; 410A , B ) in each charge-confining layers stack portion forming a charge storage element; forming side control gates ( 113A , B ; 212 ; 312 ; 413A , B ) over each of the charge-confining layers stack portions; forming memory cell source/drain regions ( 115 ; 215 ; 315 ; 415 ) laterally to the side control gates; electrically connecting ( 116 , 117 ; 216 ; 312 ; 416 ) the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an "L" shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

    Abstract translation: 一种用于制造双电荷存储位置电可编程存储器单元的工艺包括以下步骤：在半导体衬底（11）上形成中央绝缘栅极（12,15）; 在中央栅极的侧面处形成物理分离的电荷限制层堆叠电介质电荷俘获材料 - 电介质层堆叠（19,110,111; 29,210,211; 49A，B，410A，B，411A，B）部分，电荷俘获材料层 （110; 210; 410A，B）在每个电荷限制层堆叠部分中形成电荷存储元件; 在每个电荷限制层堆叠部分上方形成侧控制栅极（113A，B; 212; 312; 413A，B） 在所述侧控制栅极的侧面形成存储器单元源极/漏极区域（115; 215; 315; 415） 将所述侧控制栅极电连接到所述中央栅极（116,117; 216; 312; 416）。 中央栅极侧的每个电荷限制层堆叠部分形成为“L”形，其中基础电荷限制层堆叠部分位于衬底表面上，并且竖直电荷限制层堆叠部分抵靠 绝缘栅极的相应侧。

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