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    Stabilisation method of the drain voltage in non-volatile multilevel memory cells and relating memory device
    2.
    发明公开
    Stabilisation method of the drain voltage in non-volatile multilevel memory cells and relating memory device 有权
    一种用于在非易失性存储器的稳定具有多状态存储器设备和相关联的漏极电压的方法

    公开(公告)号：EP1435623A1

    公开(公告)日：2004-07-07

    申请号：EP02425801.4

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Crippa, Luca ,  Ragone, Giancarlo

    IPC: G11C16/10

    CPC classification number: G11C16/12 ,  G11C11/5628

    Abstract: The present invention relates to a method and an electronic device for stabilising the voltage on the drain terminals of multilevel non volatile memory cells (3) in the programming step. In the method the application of said voltage is provided through a drain voltage regulator (2) having an output (OUT) connected to said terminals in a common circuit node (A) by means of a metal line (4) conduction path having a parasitic intrinsic resistance (R pars ). Advantageously, a feedback path (5) is provided between the node (A) and an input of the regulator (2).

    Abstract translation: 本发明涉及一种用于在电子稳定性伊辛上在编程步骤的多级非易失性存储器单元（3）的漏极端子处的电压的方法和设备。 在该方法中，所述电压的施加是通过在由金属线的方式共同的电路节点（A）连接到所述端子的漏极电压调节器（2），其具有在输出端（OUT）提供了具有寄生（4）导通路径 固有电阻（Rpars）。 有利地，所述节点（A）之间以及在调节器（2）的输入端提供的反馈路径（5）。

    Page buffer for multi-level NAND programmable memories
    4.
    发明公开
    Page buffer for multi-level NAND programmable memories 有权
    Multipegel-NAND-Speicher的程序设计师Seitenspeicher

    公开(公告)号：EP1748445A1

    公开(公告)日：2007-01-31

    申请号：EP05106972.2

    申请日：2005-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC: G11C11/56

    CPC classification number: G11C11/5628

    Abstract: A page buffer (130) for an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in a plurality of bit lines (BLe,BLo) of memory cells and forming a plurality of individually-selectable memory sets. The electrically programmable memory includes a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (MSB) and a second data bits group (LSB), the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets forming at least a first memory page and a second memory page, respectively. The first and second memory pages are individually addressable in reading and writing. The page buffer comprises at least one read/program unit (205) having a coupling line (SO) operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cells sets. The read/program unit comprises enabling means (230-1, 230-2, 252, 254, 256, 258, 272, 274, 276, 278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits (MSB) of the selected memory cell, and an existing data value already stored in the second group of data bits (LSB) of the selected memory cell. The enabling means comprise reading means (256, 258, 260, 230-2) for retrieving the existing data value; means (252, 254, 230-1) for receiving an indication of the target data value; combining means (272, 274, 276, 278) for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication; and conditioning means (272, 274) included in the combining means for conditioning a potential of the coupling line based on the existing data value and the modified indication, so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

    Abstract translation: 提供了一种用于电可编程存储器（100）的页缓冲器（130）。 电可编程存储器包括布置在存储器单元的多个位线（BLe，BLo）中的多个存储单元（110），并形成多个单独选择的存储器组。 电可编程存储器包括针对每个存储器单元定义的多个不同的编程状态，对应于每个存储单元中可存储的数据位数N> = 2。 数据位包括至少第一数据位组（MSB）和第二数据位组（LSB），第一数据位组和分别存储在所述可单独选择的一个存储单元中的第二数据位组 存储单元组分别形成至少第一存储器页面和第二存储器页面。 第一和第二个存储器页面在读取和写入时可单独寻址。 页面缓冲器包括至少一个具有可操作地与至少一个所述位线相关联的耦合线（SO）的读/写单元（205），并且适于至少临时存储从或写入 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置（230-1,230-2,252,254,256,258,272,274,276,278,278,276,278,272,276,278,276,278,278,276,278,276,278,278,276,278,278,276,278,278,276,278,278,276,278,278,278,276,278,278,278,276,278,278,2 行程序中的一个，使程序启用电位和程序禁止电位，调节为要存储在所选择的存储器单元的第一组数据位（MSB）中的目标数据值，以及已经存储在第二个存储单元中的现有数据值 所选存储单元的数据位组（LSB）组。 启用装置包括用于检索现有数据值的读取装置（256,258,260,230-2）; 用于接收目标数据值的指示的装置（252,254,230-1）; 用于将接收到的目标数据值与所检索的现有数据值组合的组合装置（272,274,276,278），从而修改目标数据值的所述指示以获得修改的指示; 以及包括在组合装置中的调节装置（272,274），用于基于现有数据值和修改的指示调节耦合线的电位，以使耦合线采取程序使能电位或编程抑制电位 。

    Charge-pump type voltage-boosting device with reduced ripple, in particular for non-volatile flash memories
    5.
    发明公开
    Charge-pump type voltage-boosting device with reduced ripple, in particular for non-volatile flash memories 审中-公开
    电荷泵型电压失真减小尤其是对于非易失性快闪存储器的电压提升电路

    公开(公告)号：EP1727146A1

    公开(公告)日：2006-11-29

    申请号：EP05425348.9

    申请日：2005-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Sangalli, Miriam ,  Crippa, Luca ,  Micheloni, Rino

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

    CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073 ,  H02M2001/007

    Abstract: Voltage-boosting device having a supply input (9) receiving a supply voltage (Vdd), and a high-voltage output (3). The device (1) is formed by a plurality of charge-pump stages (14) series-connected between the supply input (9) and the high-voltage output (3). Each charge-pump stage (14) has a respective enabling input receiving an enabling signal (EN1, ..., ENn-1, ENn). A control circuit (4, 8) formed by a plurality of comparators (8.1, ..., 8.n-1, 8.n) is connected to the high-voltage output (3) and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output (3) and a plurality of reference voltages (REF1, ..., ..., REFn-1, REFn), one for each comparator. The charge-pump stages (14) are grouped into sets of stages (13.1, ..., 13.n-1, 13.n), and the stages belonging to a same set receive a same enabling signal (EN1, ENn-1, ENn); thus, as many comparators as there are sets of stages are present.

    Abstract translation: 升压具有供电输入端（9），接收电源电压（Vdd）的装置，和一个高电压输出端（3）。 所述装置（1）通过的电荷泵级（14）串联连接在电源输入端（9）和所述输出高电压（3）之间形成的多个。 每个电荷泵级（14）具有一个respectivement使能输入处接收使能信号（EN1，...，ENN-1，ENN）。 控制电路（4,8）由比较器形成的多个（8.1，...，8.n.-1，8.n.）连接到高电压输出端（3）和基因率使能信号的基础上 在高电压输出端（3）的基准电压的多个电压之间的比较和（REF1，...，...，REF N-1，REF n）时，一个用于每个比较器。 电荷泵级（14）被分成组级（13.1，...，13.n-1，13.n），并且属于同一组的各个阶段接收相同的使能信号（EN1，ENn- 1，ENN）; 因此，许多比较，因为有套阶段都存在。

    Multistage regulator for charge-pump boosted voltage applications
    9.
    发明公开
    Multistage regulator for charge-pump boosted voltage applications 有权
    MehrstufenreglerfürLadungspumpen在Spannungserhöhungsanwendungen

    公开(公告)号：EP1750271A1

    公开(公告)日：2007-02-07

    申请号：EP05425558.3

    申请日：2005-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Sangalli, Miriam ,  Ragone, Giancarlo ,  Micheloni, Rino

    IPC: G11C5/14 ,  G11C16/30

    CPC classification number: G11C5/145 ,  G11C16/30

    Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance (C LOAD ) of an integrated device at a certain charge-pump generated boosted voltage is safely implemented without obliging to integrate high voltage transistor structures of type of conductivity of the same sign of the boosted voltage (high-side transistors).
    Another fulfilled objective is to provide a multilevel nonvolatile flash memory device comprising a boosted voltage regulator that can be entirely fabricated with a low cost nonvolatile flash memory fabrication process.
    Basically, the multistage circuit for regulating the charge voltage or the discharge current of a capacitance in an integrated device, comprising at least a first stage and an output stage in cascade to the first stage and coupled to the capacitance, has the first stage supplied at an unboosted power supply voltage (V DD ) of the integrated device and the output stage supplied at an unregulated charge-pump generated boosted voltage (V PUMP ) and is composed of a transistor (M NOUT ) of type of conductivity opposite to the sign of the boosted voltage and of the power supply voltage.
    The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up (R PULL-UP ) or a voltage limiter.

    Abstract translation: 在一定的电荷泵产生的升压电压下，用于调节集成器件的电容（C LOAD）的充电电压或放电电流的多级电路被安全地实现，而不必集成将相同电导率的高电压晶体管结构 升压电压（高侧晶体管）的符号。 另一个实现的目标是提供一种多级非易失性闪存器件，其包括可以用低成本的非易失性闪速存储器制造工艺完全制造的升压型稳压器。 基本上，用于调节集成装置中的电容的充电电压或放电电流的多级电路包括至少第一级和级联到第一级并耦合到电容的输出级，第一级提供在 该集成装置的未升压的电源电压（V DD）和在未调节的电荷泵产生的升压电压（V PUMP）下提供的输出级，并且由一个导体类型的晶体管（M NOUT）构成， 升压电压和电源电压。 输出级晶体管的漏极通过电阻上拉（R PULL-UP）或限压器耦合到升压电压。

    Read circuit for a nonvolatile memory
    10.
    发明公开
    Read circuit for a nonvolatile memory 有权
    发言人LeseschaltungfüreinennichtflüchtigenSpeicher

    公开(公告)号：EP1071096A1

    公开(公告)日：2001-01-24

    申请号：EP99830469.5

    申请日：1999-07-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Crippa, Luca

    IPC: G11C16/28 ,  G11C7/06

    CPC classification number: G11C16/28

    Abstract: The read circuit (1') comprises an array branch (6) having an input array node (22) connected, via an array bit line (8), to an array cell (10); a reference branch (12) having an input reference node (32) connected, via a reference bit line (14), to a reference cell (16); a current-to-voltage converter (18) connected to an output array node (56) of the array branch (6) and to an output reference node (58) of the reference branch (12) to supply on the output array node (56) and the output reference node (58) the respective electric potentials (V M , V R ) correlated to the currents flowing in the array memory cell (10) and, respectively, in the reference memory cell (16); and a comparator (19) connected at input to the output array node (56) and output reference node (58) and supplying as output a signal (OUT) indicative of the contents stored in the array memory cell (10); and an array decoupling stage (80) arranged between the input array node (22) and the output array node (56) to decouple the electric potentials of the input and output array nodes (22, 56) from one another.

    Abstract translation: 读取电路（1'）包括具有通过阵列位线（8）连接到阵列单元（10）的输入阵列节点（22）的阵列分支（6）。 具有通过参考位线（14）连接到参考单元（16）的输入参考节点（32）的参考分支（12）; 连接到阵列分支（6）的输出阵列节点（56）和参考分支（12）的输出参考节点（58）的电流 - 电压转换器（18），以在输出阵列节点 56）和输出参考节点（58）分别与在阵列存储单元（10）中流动的电流和参考存储单元（16）相关的电位相关联的各个电位（VM，VR）; 以及比较器（19），其在输入端连接到输出阵列节点（56）和输出参考节点（58），并且作为输出提供指示存储在阵列存储单元（10）中的内容的信号（OUT）。 以及布置在所述输入阵列节点（22）和所述输出阵列节点（56）之间的阵列解耦级（80），以将所述输入和输出阵列节点（22,56）的电位彼此去耦。

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