中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

92 records (took 0.047 seconds)

    Semiconductor memory with embedded dram
    6.
    发明公开
    Semiconductor memory with embedded dram 有权
    带有嵌入式DRAM存储器的半导体存储器

    公开(公告)号：EP1422719A3

    公开(公告)日：2005-04-27

    申请号：EP03103920.9

    申请日：2003-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  MICHELONI, Rino

    IPC: G11C11/00

    CPC classification number: G11C11/005

    Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

    power supply circuit structure for a row decoder of a multilevel non-volatile memory device
    7.
    发明公开
    power supply circuit structure for a row decoder of a multilevel non-volatile memory device 有权
    多功能三极管

    公开(公告)号：EP1434233A1

    公开(公告)日：2004-06-30

    申请号：EP02029093.8

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56

    CPC classification number: G11C11/5621 ,  G11C8/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/30

    Abstract: The invention relates to a power supply circuit structure useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and switching means for transferring said voltages over hierarchic-mode enabled conduction paths are provided.

    Abstract translation: 本发明涉及一种与行解码器有用的电源电路结构，用于从包含多电平存储器单元的阵列的集成电可编程/可擦除非易失性存储器件读/写存储单元的数据。 有利地，提供了对于行解码器和切换装置的多个电源电压，用于在分层模式使能的传导路径上传送所述电压。

    Integrated electronic device with reduced internal connections
    10.
    发明公开
    Integrated electronic device with reduced internal connections 审中-公开
    Integrierte elektronische Anordnung mit verminderten internen Verbindungen

    公开(公告)号：EP1189234A1

    公开(公告)日：2002-03-20

    申请号：EP00830617.7

    申请日：2000-09-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C5/06

    CPC classification number: G11C5/066

    Abstract: The integrated electronic device (10) with reduced internal connections comprises a first memory device (11), having signal pins (11a, 11d), data pins (11b 1 ), and an enabling pin (11c) receiving a first enabling signal (CE1), and a second memory device (12) having signal pins (12a, 12d), data pins (12b 1 ), and an enabling terminal (12c) receiving a second enabling signal (CE2). The signal pins (12a, 12d) of the second memory device (12) are connected directly to corresponding data pins (11b 1 ) of the first memory device (11). In addition, the first memory device (11) comprises first connecting means (19), which can be activated selectively in order to define a current path between each signal pin (11a, 11d) and each data pin (11b 1 ), and the second memory device (12) comprises second connecting means (22), which can be activated selectively in order to define a current path between each signal pin (12a, 12d) and each data pin (12b 1 ).

    Abstract translation: 具有减小的内部连接的集成电子设备（10）包括具有信号引脚（11a，11d），数据引脚（11b1）和接收第一使能信号（CE1）的使能引脚（11c）的第一存储器件（11） 以及具有信号引脚（12a，12d），数据引脚（12b1）和接收第二使能信号（CE2）的使能终端（12c）的第二存储器件（12）。 第二存储器件（12）的信号引脚（12a，12d）直接连接到第一存储器件（11）的相应数据引脚（11b1）。 另外，第一存储器件（11）包括第一连接装置（19），其可被选择性地激活，以便限定每个信号引脚（11a，11d）和每个数据引脚（11b1）之间的电流路径，而第二连接装置 存储器件（12）包括第二连接装置（22），其可被选择性地激活，以便限定每个信号引脚（12a，12d）和每个数据引脚（12b1）之间的电流路径。

Patent Agency Ranking