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    A memory device with row selector comprising series connected medium voltage transistors
    4.
    发明公开
    A memory device with row selector comprising series connected medium voltage transistors 有权
    在意大利语中的Speichervorrichtung mit einem Zeilenselektor mit Mantelspannungstransistoren

    公开(公告)号：EP1892724A1

    公开(公告)日：2008-02-27

    申请号：EP06119440.3

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C16/08 ,  G11C8/08

    CPC classification number: G11C16/08

    Abstract: A non-volatile memory device is provided. The memory device includes a memory matrix (105; 605) comprising a plurality of memory cells (Mc), arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines (WL(i)); each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet (WLP). The memory device includes a row selector (160; 660) coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first (N(i)) and a second (P(i)) selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means (110) for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means (150) for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.

    Abstract translation: 提供非易失性存储器件。 存储器件包括存储器矩阵（105; 605），其包括根据多行和多列布置的多个存储器单元（Mc）。 存储装置还包括多个字线（WL（i））; 每个字线与所述多个的一个相应行相关联，并连接到该行的存储单元; 字线被分组成至少一个分组（WLP）。 存储器件包括耦合到字线并适于选择性地偏置它们的行选择器（160; 660）。 行选择器对于每个字线分组包括多个第一路径，其中每个第一路径适于根据要连接的存储器单元执行的操作将第一偏置电压施加到分组的对应字线 到相应的字线。 每个第一路径包括串联连接在第一路径的第一终端和第二终端之间的至少第一（N（i））和第二（P（i））选择晶体管。 第二终端耦合到对应的字线。 存储器件还包括用于共同地向包括所选择的字线的所选择的字线分组的第一路径的第一终端提供使能电压的启用装置（110）。 使能电压取决于对连接到所选字线的存储器单元执行的操作，并且适于使得能够执行所述操作。 存储装置还包括用于选择所述多个第一路径之一的选择装置（150）。 所选择的第一路径对应于所选择的字线。 选择装置适于激活所选择的第一路径的第一选择晶体管，以便通过由第一选择晶体管引入的电压降从使能电压获得第一偏置电压; 所述选择装置还适于激活所选择的第一路径的第二选择晶体管，以便将由第一选择晶体管提供的第一偏置电压传送到所选择的字线上。

    Improvements to the design of voltage switches
    5.
    发明公开
    Improvements to the design of voltage switches 有权
    Verbesserungen am Entwurf von Spannungsschalter

    公开(公告)号：EP1837993A1

    公开(公告)日：2007-09-26

    申请号：EP06111477.3

    申请日：2006-03-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

    CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

    Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

    Abstract translation: 公开了一种电路。 该电路包括第一输入端（INA1），第二输入端（INA2）和输出端（OUT）。 电路还包括连接在第一输入端和输出端之间的第一电路分支（610）和连接在第二输入端和输出端之间的第二电路分支（620）。 第一电路分支可选择性地激活用于将第一输入端子与输出端子耦合，并且第二电路支路选择性地激活以将第二输入端子与输出端子耦合。 第一和第二电路分支包括每个至少一个具有至少第一和第二设备端子的电子设备。 所述至少一个电子设备被设计成保证在至少其第一和第二设备端子之间保持电压差的能力，所述第一和第二设备端子的绝对值上限受到低于电压差绝对值的最大值的第一预定最大值的限制 在输出端子和第一输入端子之间以及输出端子和第二输入端子之间。

    Data control unit capable of correcting boot errors, and corresponding method
    7.
    发明公开
    Data control unit capable of correcting boot errors, and corresponding method 有权
    DatenverwaltungseinheitfähigStartfehler zu korrigieren und entsprechendes Verfahren

    公开(公告)号：EP1607865A1

    公开(公告)日：2005-12-21

    申请号：EP04425436.5

    申请日：2004-06-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Babudri, Irene ,  Roveda, Marco ,  Micheloni, Rino

    IPC: G06F11/14

    CPC classification number: G06F11/1417 ,  G06F11/076

    Abstract: Boot method for a data control unit, wherein boot information is downloaded from a nonvolatile memory (22) into a temporary buffer (29) of a boot-activation unit (21); a processing unit (23) is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory (22) into a volatile memory (24) through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit (21) verifies whether the boot information downloaded into its volatile memory (24) has a critical-error condition and activates a spare memory portion (37) of the nonvolatile memory (22) in presence of the critical-error condition.

    Abstract translation: 一种用于数据控制单元的引导方法，其中引导信息从非易失性存储器（22）下载到引导启动单元（21）的临时缓冲器（29）中; 处理单元（23）由引导启动单元激活; 由处理单元执行引导代码; 并且通过引导启动单元将操作代码从非易失性存储器（22）下载到易失性存储器（24）中。 为了校正包含信息和引导代码的非易失性存储器的块中的可能错误，启动激活单元（21）验证下载到其易失性存储器（24）中的引导信息是否具有关键错误状况并激活备用存储器部分 （22）的非易失性存储器（37）存在临界误差条件。

    Integrated memory system comprising at least a non-volatile memory and an automatic error corrector
    8.
    发明公开
    Integrated memory system comprising at least a non-volatile memory and an automatic error corrector 审中-公开
    集成存储器系统具有至少一个非易失性存储器以及一个自动误差校正器

    公开(公告)号：EP1460542A1

    公开(公告)日：2004-09-22

    申请号：EP03425171.0

    申请日：2003-03-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasio, Roberto

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1048

    Abstract: The present invention relates to an integrated memory system (1) comprising at least a non volatile memory (2) and an automatic storage error corrector, and wherein the memory (2) is connected to a controller (3) by means of an interface bus (4). Advantageously, the system comprises in the memory (2) circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal (IRQ) to ask a correction being external to the memory (2).

    Abstract translation: 本发明涉及到集成存储系统（1），包括至少一个非易失性存储器（2）和自动存储误差校正器，和worin存储器（2）通过接口总线连接到控制器（3） （4）。 有利地，该系统包括：在存储器（2）的电路装置，在功能上独立的，每个负责一个预定的存储误差的修正; 产生一个信号（IRQ）问的校正是外部存储器。所述装置的至少一个（2）。

    Method for replacing failed non-volatile memory cells and corresponding memory device
    9.
    发明公开
    Method for replacing failed non-volatile memory cells and corresponding memory device 有权
    一种用于替换失效非易失性存储单元和相应的存储器阵列的方法

    公开(公告)号：EP1403879A1

    公开(公告)日：2004-03-31

    申请号：EP02425591.1

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C29/00 ,  G11C16/16

    CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

    Abstract: The invention relates to a method for replacing failed non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array (4) organized in a row-and-column layout, and divided in array sectors (20), including at least one row decode circuit portion being supplied positive and negative voltages (Vpcx,HVNEG).
    The method is applied whenever the result of the erase algorithm is negative, and comprises the following steps:-

    forcing an incompletely erased sector (20) into a read condition;
    scanning the rows of said sector (20) to check for the possible presence of a spurious current indicating a fail state;
    identifying and electrically isolating the failed row;
    re-addressing from said failed row to a redundant row provided in the same sector (20);
    re-starting the erase algorithm.

    Abstract translation: 该方法包括迫使完全擦除扇区负进一个阅读条件，只要擦除算法的问题是不完整的或。 该部门的行进行扫描，以检查虚假电流指示了失效的可能存在。 失败的行识别和电气隔离。 该失效行重新给在同一个部门重新启动算法提供一个冗余行。 因此独立claimsoft被包括为综合的非易失性存储器设备。

    Use of an error correction circuit in program and erase verify procedures
    10.
    发明公开
    Use of an error correction circuit in program and erase verify procedures 有权
    Benutzung einer Fehlerkorrektionsschaltung在Programmierungs-undLöschverifikation

    公开(公告)号：EP1355234A1

    公开(公告)日：2003-10-22

    申请号：EP02425231.4

    申请日：2002-04-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Losavio, Aldo

    IPC: G06F11/10 ,  G11C16/34

    CPC classification number: G06F11/1068

    Abstract: The method for using a nonvolatile memory (1) having a plurality of cells (14), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming (22) the data of the memory; verifying (23) the correctness of the data of the memory cells; and, if the step of verifying (23) has revealed at least one incorrect datum, correcting on-th-field (46) the incorrect datum, using an error correcting code. The verification (23) of the correctness of the data is performed by determining (23) the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold (46), the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

    Abstract translation: 使用具有存储数据的多个单元（14）的非易失性存储器（1）的方法基于执行擦除/编程（22）存储器的数据的修改操作的步骤; 验证（23）存储器单元的数据的正确性; 并且如果验证（23）的步骤已经显示至少一个不正确的数据，则使用错误校正码校正不正确的数据（46）。 通过确定（23）存储不正确数据的存储单元的数量来执行数据正确性的验证（23） 如果存储不正确的数据的存储单元的数量小于或等于阈值（46），则错误校正码校正错误的数据; 否则，将提供新的擦除/编程脉冲。

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