公开(公告)号：EP4212894A1

公开(公告)日：2023-07-19

申请号：EP22215074.0

申请日：2022-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： DE CAMPO, Nicola ,  VENTURELLI, Matteo ,  BRIVIO, Matteo ,  FOPPIANI, Mauro

IPC: G01R31/28

Abstract: A system for testing comprising an electronic circuit to be tested (11) and an automatic testing equipment (12),
said electronic circuit (11) to be tested comprising a voltage monitor (110) to be tested comprising a resistive divider (111) receiving at its voltage input an input voltage (VIN) to be monitored and coupled at its output to an input of a comparator (113), a reference input of said comparator (113) being coupled to a reference voltage generator (112) supplying a reference voltage (VREF) setting one or more thresholds of the comparator (113),
wherein said electronic circuit (11) to be tested comprises a Built In Self Test Module (114) coupled to said Automatic Test Equipment (12) and to the inputs and output of said comparator (113), said BIST module (114) being configured upon receiving respective commands from the Automatic Test Equipment (12) to test a reaction time (D LH , D HL ) of the comparator (113) and an offset (VOFS) of the comparator (113),
said Automatic Test Equipment (12) comprising means (125, 126, 127, 128, 129) for performing a respective test of the ratio of the resistor divider (111) by a first voltage measurement (128) of a voltage between an input of the divider (111) and the output of the divider (111) and a test of the reference voltage (VREF) provided by the reference threshold generator (112) by a second voltage measurement (129) of the voltage applied by the reference threshold generator (112) at the reference input node of the comparator (113).

公开(公告)号：EP4148436A1

公开(公告)日：2023-03-15

申请号：EP22192346.9

申请日：2022-08-26

Applicant: STMicroelectronics S.r.l.

Inventor： BRIVIO, Matteo ,  DE CAMPO, Nicola ,  VENTURELLI, Matteo

IPC: G01R31/3187 ,  G01R31/3185 ,  G01R31/317

Abstract: A system for testing comprising an electronic circuit to be tested and an automatic testing equipment,
said electronic circuit (10; 10'; 10"; 10‴) to be tested comprising a stage (122a, 122b) configured to supply a driving signal to a load, said stage (122a, 122b) comprising a pullup switch (122a) coupled to the voltage supply (VS) and a pulldown switch coupled to a lower potential than the voltage supply (GND, S), in particular ground, coupled to each other in an output node (G), and a pre-driver stage (12) comprising pre-driver circuits (121a, 121b) which output is coupled to the control input of respective pullup (122a) and pull down (122b) switch of the stage (122a, 122b) configured to supply a driving signal to a load,
said electronic circuit (10; 10'; 10"; 10‴) to be tested comprising circuits (11, 14) for testing the pre-driver stage (12) under the control (SCMD) of the automatic testing equipment (20; 20'; 20"; 20‴) comprising a test logic module (11) configured to operate a built-in test sequence comprising test commands (PU CMD, PD CMD) for the pre-driver stage under the control of an external test signal (SCMD) issued by the automatic test equipment, the automatic test equipment (20, 20', 20") comprising a test load (211) to be coupled to said output node (G) of the stage (122a, 122b) configured to supply a driving signal to a load, said system for testing comprising a time measuring unit (14) configured to measure duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load coupled to a pass fail check module (145), configured to evaluate if said duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load satisfies a pass criterion,
wherein
said time measuring unit (14) is comprised in said electronic circuit to be tested and it started and stopped under the control of commands including commands ((PU CMD, PD CMD, SEL) issued by said logic (11) during execution of said bult-in test sequence.

公开(公告)号：EP4068604A1

公开(公告)日：2022-10-05

申请号：EP22163173.2

申请日：2022-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： VENTURELLI, Matteo ,  DE CAMPO, Nicola

IPC: H02M3/07 ,  H03K17/06

Abstract: A circuit (51) for regulating a voltage (V IN ) received at its input comprising
a configurable voltage regulating circuit (52) comprising
a first switch (S 1 ) coupled between the input node (I) and a common node (CM), a second switch (S 2 ) being coupled between said common node (CM) and a ground node (GND),
a flying capacitor (CFLY) coupled between the common node (CM) and a pump node (CP),
a third switch (S 3 ) coupled between the input node (I) and a pump node (C P )and a fourth switch coupled between the pump node (C P )and an output node (O) of the circuit (51) for regulating a voltage (V IN ),
the circuit further comprising a sense resistance network (55), in particular a resistance divider, coupled between the output node (O) and the input of an error amplifier (56) to provide at such input a sensed output voltage (VDIV_OUT), said error amplifier (56) receiving at its other input a reference voltage (VREF) and generating an error signal (E),
a charging circuit (57; 67) supplying a charging current (I CTRL ) to said pump node (CP), said charging circuit (I CTRL ) controlling the value of said charging current (I CTRL ) as a function of said error control signal (E),
a generator of switch command signals (54) configured to generate respective first, second, third and fourth switch signal to control respectively said first switch (S 1 ), second switch (S 2 ), third switch (S 3 ) fourth switch (S 4 ), said generator (54) if the input voltage is lower than a first threshold said generator (54) being configured to set the configurable voltage regulating circuit (52) as charge pump by generating the first (CLKNS 1 ) and second switch signal (CLKS 2 ) driven by opposite phases of a clock signal (CLK) to couple alternatively the common mode to the input voltage and the ground, the third (CLKS 3 ) and fourth switch signal (CLKNS 4 ) are driven by opposite phases of said clock signal (CLK) to couple alternatively the pump node (C P )to the output node (O) and to the charging circuit (57; 67),
if the input voltage is greater than a second threshold said generator (54) being configured to set the configurable voltage regulating circuit (52) as linear regulator by generating a first switch signal (CLKNS 1 ) keeping the first switch (S 1 ) open and a second, third and fourth switch signal (CLKS 2 , CLKS 3 , CLKNS 4 ) keeping the second (S 2 ), third (S 3 ) and fourth (S 4 ) switch closed.

公开(公告)号：EP4113845A1

公开(公告)日：2023-01-04

申请号：EP22178676.7

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： BENDOTTI, Valerio ,  DE CAMPO, Nicola ,  CURINA, Carlo

IPC: H03K19/0185 ,  H04L25/02

Abstract: A transmitter circuit (802') receives a PWM input signal ( PWM IN ) and a clock signal ( CLK ) . A logic circuit (805) generates a control signal ( TX DIS ) as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than half clock period of the clock signal. A tri-state transmitter (802) receives the PWM input signal and the control signal, and produces a first ( OUT P ) and a second ( OUT N ) output signals at a first (802P) and a second (802N) transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage ( V DD ) and a reference voltage ( V SS ) . An output control circuit (806) is sensitive to the control signal and is coupled to the first and second transmitter output nodes. In response to the control signal being high, the tri-state transmitter sets the first and second transmitter output nodes to a high impedance state, and the output control circuit drives the first and second transmitter output nodes to an intermediate voltage ( V X ) between the positive voltage and the reference voltage. In response to the control signal being low, the tri-state transmitter drives the first transmitter output node according to the logic value of the PWM input signal, and drives the second transmitter output node according to the inverted logic value of the PWM input signal. The tri-state transmitter is faster than the output control circuit in driving the first and second transmitter output nodes.