公开(公告)号：EP4212894A1

公开(公告)日：2023-07-19

申请号：EP22215074.0

申请日：2022-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： DE CAMPO, Nicola ,  VENTURELLI, Matteo ,  BRIVIO, Matteo ,  FOPPIANI, Mauro

IPC: G01R31/28

Abstract: A system for testing comprising an electronic circuit to be tested (11) and an automatic testing equipment (12),
said electronic circuit (11) to be tested comprising a voltage monitor (110) to be tested comprising a resistive divider (111) receiving at its voltage input an input voltage (VIN) to be monitored and coupled at its output to an input of a comparator (113), a reference input of said comparator (113) being coupled to a reference voltage generator (112) supplying a reference voltage (VREF) setting one or more thresholds of the comparator (113),
wherein said electronic circuit (11) to be tested comprises a Built In Self Test Module (114) coupled to said Automatic Test Equipment (12) and to the inputs and output of said comparator (113), said BIST module (114) being configured upon receiving respective commands from the Automatic Test Equipment (12) to test a reaction time (D LH , D HL ) of the comparator (113) and an offset (VOFS) of the comparator (113),
said Automatic Test Equipment (12) comprising means (125, 126, 127, 128, 129) for performing a respective test of the ratio of the resistor divider (111) by a first voltage measurement (128) of a voltage between an input of the divider (111) and the output of the divider (111) and a test of the reference voltage (VREF) provided by the reference threshold generator (112) by a second voltage measurement (129) of the voltage applied by the reference threshold generator (112) at the reference input node of the comparator (113).

公开(公告)号：EP4175181A1

公开(公告)日：2023-05-03

申请号：EP22200971.4

申请日：2022-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： PEDONE, Leonardo ,  SCADUTO, Simone ,  GAUDIANO, Rossella ,  BRIVIO, Matteo ,  VENTURELLI, Matteo

IPC: H03M1/10

Abstract: A system for testing comprising an electronic circuit to be tested (11; 11'; 11"; 11‴) and an automatic testing equipment (12; 12'),
said electronic circuit (11; 11'; 11"; 11‴) to be tested comprises a digital to analog converter (111; 111';111"), comprising
a set of electronic components (R; I), in particular arranged in a network, coupled to an analog reference voltage or to an analog reference current and
a multiplexing network of switches (111b) coupled to said set of electronic components (R;I) and configured to select paths in said set of electronic components (R;I) on the basis of digital values (DC) at the input of said digital to analog converter (111; 111';111") supplied by a logic control module (112) comprised in said electronic circuit (11; 11'; 11"; 11‴),
said electronic circuit (11; 11'; 11"; 11‴) to be tested comprising an input data link (113b, 123b) between the automatic testing equipment (20, 20', 20") and the logic control module (112),
the system for testing being configured to perform a test of the set of electronic components (R;I) in which the automatic testing equipment (20, 20', 20") is configured to send digital data (TD) to control the logic module (112) inputting digital codes (DC) in the digital to analog converter (111; 111';111") and measuring the analog output of the digital to analog converter (111; 111';111") by a measuring instrument (122; 122') in said automatic testing equipment (12;12') coupled to an output (VDAC, Vin) of the electronic circuit (10, 10', 10‴), then checking if the measured values matches expected converted values for the given digital data (TD),
wherein said test of the digital to analog converter (111; 111'; 111") comprises a further test of the multiplexing network of switches (111b) in which
said logic module (112) is configured to execute a built-in test sequence (300) comprising supplying by said logic module (112) a sequence of digital codes (DC) forcing given switches of said multiplexing network of switches (111b) in a determined open or close state,
said electronic circuit (11'; 11"; 11‴) comprising a feedback circuit (111d) to supply a feedback signal (FB) to said logic module (112), said logic module (112) being configured, on the basis of said feedback signal (FB), to control an execution flow of the built-in test sequence (300)) and to verify (324, 325) if the feedback signal (TB) matches an expected value for the corresponding digital code (DC) in the sequence of digital codes.

公开(公告)号：EP4148436A1

公开(公告)日：2023-03-15

申请号：EP22192346.9

申请日：2022-08-26

Applicant: STMicroelectronics S.r.l.

Inventor： BRIVIO, Matteo ,  DE CAMPO, Nicola ,  VENTURELLI, Matteo

IPC: G01R31/3187 ,  G01R31/3185 ,  G01R31/317

Abstract: A system for testing comprising an electronic circuit to be tested and an automatic testing equipment,
said electronic circuit (10; 10'; 10"; 10‴) to be tested comprising a stage (122a, 122b) configured to supply a driving signal to a load, said stage (122a, 122b) comprising a pullup switch (122a) coupled to the voltage supply (VS) and a pulldown switch coupled to a lower potential than the voltage supply (GND, S), in particular ground, coupled to each other in an output node (G), and a pre-driver stage (12) comprising pre-driver circuits (121a, 121b) which output is coupled to the control input of respective pullup (122a) and pull down (122b) switch of the stage (122a, 122b) configured to supply a driving signal to a load,
said electronic circuit (10; 10'; 10"; 10‴) to be tested comprising circuits (11, 14) for testing the pre-driver stage (12) under the control (SCMD) of the automatic testing equipment (20; 20'; 20"; 20‴) comprising a test logic module (11) configured to operate a built-in test sequence comprising test commands (PU CMD, PD CMD) for the pre-driver stage under the control of an external test signal (SCMD) issued by the automatic test equipment, the automatic test equipment (20, 20', 20") comprising a test load (211) to be coupled to said output node (G) of the stage (122a, 122b) configured to supply a driving signal to a load, said system for testing comprising a time measuring unit (14) configured to measure duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load coupled to a pass fail check module (145), configured to evaluate if said duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load satisfies a pass criterion,
wherein
said time measuring unit (14) is comprised in said electronic circuit to be tested and it started and stopped under the control of commands including commands ((PU CMD, PD CMD, SEL) issued by said logic (11) during execution of said bult-in test sequence.