公开(公告)号：EP1225597A1

公开(公告)日：2002-07-24

申请号：EP01830016.0

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Frulio, Massimiliano ,  Villa, Corrado ,  Bartoli, Simone

IPC: G11C16/32 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/32

Abstract: Described herein is a nonvolatile memory (10) comprising an input pin (2) receiving an external clock signal (CK EST ) supplied by a user; an input buffer (4) receiving the external clock signal (CK EST ) and supplying an intermediate clock signal (CK INT1 ) delayed with respect to the external clock signal (CK EST ); and a delay locked loop (12) receiving the intermediate clock signal (CK INT1 ) and supplying an internal clock signal (CK INT ) distributed within the nonvolatile memory (10) and substantially in phase with the external clock signal (CK EST ).

Abstract translation: 这里描述的是一种非易失性存储器（10），包括接收由用户提供的外部时钟信号（CKEST）的输入引脚（2） 接收外部时钟信号（CKEST）并提供相对于外部时钟信号（CKEST）延迟的中间时钟信号（CKINT1）的输入缓冲器（4）; 以及接收中间时钟信号（CKINT1）并提供分配在非易失性存储器（10）内并与外部时钟信号（CKEST）基本相位的内部时钟信号（CKINT）的延迟锁定环路（12）。