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    A non-volatile memory with a charge pump with regulated voltage
    1.
    发明公开
    A non-volatile memory with a charge pump with regulated voltage 审中-公开
    非易失性存储器，包括具有已调节电压的电荷泵

    公开(公告)号：EP1176603A1

    公开(公告)日：2002-01-30

    申请号：EP00830529.4

    申请日：2000-07-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Emanuele ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Bartoli, Simone

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: The memory comprises a matrix of cells (10), a charge pump (11), a voltage regulator, controllable connection elements (12) each connected between the output of the charge pump (11) and a column line of the matrix of cells, and means (14) for selectively activating the connection elements.
    To arrange for the voltage of a cell in a predetermined biasing condition, for example, the programming condition, to be independent of temperature variations and of manufacturing and design parameters, the memory comprises a first element (12') equivalent to a connection element (12) and a second element (10') equivalent to a memory cell (10) in the predetermined biasing condition. These equivalent elements are connected in series with one another between the output terminal and the common terminal of the charge pump (11). The regulator (15, 17) is connected between the second equivalent element (10') and the input of the charge pump (11) in order to regulate the output voltage of the charge pump (11) in dependence on the voltage across the second equivalent element (10').

    Abstract translation: 所述存储器包括单元的矩阵（10），一个电荷泵（11），电压调节器，可控制连接件（12），每个连接在所述电荷泵的输出端（11）和单元的矩阵的列线之间， 和装置（14），用于选择性激活所述连接元件。 安排在一个预定的偏状态的电池的电压，例如，编程条件，是独立的温度变化的和的制造和设计参数，所述存储器包括：第一元件（12“）等同于一个连接元件（ 12）以及等同于预定的偏状态的存储单元（10）的第二元件（10“）。 这些等效的元件被串联连接与所述输出端子和所述电荷泵（11）的公共端子之间彼此。 调节器（15，17），以便调节上横跨第二电压依赖的电荷泵（11）的输出电压连接在第二等效元件（10“）和所述电荷泵（11）的输入端之间 等效元件（10“）。

    Threshold voltage reduction of transistor shaped like a diode
    2.
    发明公开
    Threshold voltage reduction of transistor shaped like a diode 有权
    Schwerwertreduzierung eines als二极管geschalteten晶体管

    公开(公告)号：EP1071211A1

    公开(公告)日：2001-01-24

    申请号：EP99830467.9

    申请日：1999-07-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

    IPC: H03K17/06 ,  H03K17/30

    CPC classification number: H03K17/063 ,  H03K19/0027

    Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal.
    In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

    Abstract translation: 本发明涉及一种形状类似二极管的晶体管的电路处理，特别是涉及能够降低晶体管的阈值电压并等于电路处置中所用晶体管的阈值电压差的处理。 在一个实施例中，电路处理包括具有第二pMOS晶体管（301）的第一pMOS晶体管（300），第二pMOS晶体管（301）形成为类似于连接在第一晶体管的栅极和漏极之间的二极管，以及电流发生器（310） 两个晶体管。 这种电路处理也适用于nMOS晶体管。 从一般观点来看，本发明涉及通过使用串联提供电压的时间增量的电路的栅极电压增加（对于nMOS晶体管）或降低（对于pMOS晶体管）的nMOS或pMOS晶体管， 。

    Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration.
    4.
    发明公开
    Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration. 审中-公开
    该悬浮液的电变化效果期间的突发和页模式读取功能能力的非易失性存储器

    公开(公告)号：EP1073063A1

    公开(公告)日：2001-01-31

    申请号：EP99830494.3

    申请日：1999-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Russo, Antonio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/20

    Abstract: An electrically alterable semiconductor memory comprises at least two memory sectors (S1-S9) the content of which is individually alterable, and first control circuit means (4, 6) for controlling operations of electrical alteration of the content of the memory, capable of permitting the selective execution of an operation of electrical alteration of the content of one of said at least two memory sectors with the possibility of suspending said execution in order to permit read access to the other of said at least two memory sectors. The memory comprises second control circuit means (8, 6) capable of permitting, during said suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

    Abstract translation: 电可变半导体存储器包括至少两个存储器扇区（S1-S9）的所有其是独立可变的内容，以及第一控制电路装置（4,6），用于控制所述存储器的内容的电改变的操作，能够允许的 的操作的所述一个的所述内容的电改变的至少两个存储器扇区选择性执行，以便暂停所述执行的可能性，以允许读访问另一所述的至少两个存储器扇区。 所述存储器包括第二控制电路装置能够允许，所述悬浮液期间的突发模式或其他存储器扇区的内容的页面模式读取手术的（8,6）。

    Semiconductor device with selectionable pads
    5.
    发明公开
    Semiconductor device with selectionable pads 有权
    Halbleitervorrichtung mitauswälbarerAnschlussfläche

    公开(公告)号：EP1049100A1

    公开(公告)日：2000-11-02

    申请号：EP99830253.3

    申请日：1999-04-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Sali, Mauro ,  Nava, Claudio ,  Russo, Antonio

    IPC: G11C7/00 ,  G11C5/00

    CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C5/063 ,  G11C2207/105

    Abstract: Semiconductor device comprising at least two pads (101, 102; 103, 104) for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers (201, 202; 203, 204) each connected to each one of said pads, at least one multiplexer (10; 20) connected to said pads (101, 102; 103, 104) by means of said uncoupling buffers (201, 202; 203, 204) and at least one memory element (4; 5) suitable to generate a configuration signal (C ) operating on said multiplexer (10; 20) and said uncoupling buffers (201, 202; 203, 204) to selectively enable one or the other of said pads (101, 102; 103, 104).

    Abstract translation: 半导体器件包括用于输入外部信号和/或用于从所述半导体器件输出信号的至少两个焊盘（101,102; 103,104），至少两个解耦缓冲器（201,202; 203,204） 连接到所述焊盘中的每一个，至少一个通过所述解耦缓冲器（201,202; 203,204）连接到所述焊盘（101,102; 103,104）的多路复用器（10; 20）和至少一个存储器 元件（4; 5），适于产生在所述多路复用器（10; 20）和所述非耦合缓冲器（201,202; 203,204）上操作的配置信号（C），以选择性地使得所述焊盘 102; 103，104）。

    Synchronous-reading nonvolatile memory
    9.
    发明公开
    Synchronous-reading nonvolatile memory 审中-公开
    NichtflüchtigerSpeicher mit同步Lesemodus

    公开(公告)号：EP1225597A1

    公开(公告)日：2002-07-24

    申请号：EP01830016.0

    申请日：2001-01-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frulio, Massimiliano ,  Villa, Corrado ,  Bartoli, Simone

    IPC: G11C16/32 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/32

    Abstract: Described herein is a nonvolatile memory (10) comprising an input pin (2) receiving an external clock signal (CK EST ) supplied by a user; an input buffer (4) receiving the external clock signal (CK EST ) and supplying an intermediate clock signal (CK INT1 ) delayed with respect to the external clock signal (CK EST ); and a delay locked loop (12) receiving the intermediate clock signal (CK INT1 ) and supplying an internal clock signal (CK INT ) distributed within the nonvolatile memory (10) and substantially in phase with the external clock signal (CK EST ).

    Abstract translation: 这里描述的是一种非易失性存储器（10），包括接收由用户提供的外部时钟信号（CKEST）的输入引脚（2） 接收外部时钟信号（CKEST）并提供相对于外部时钟信号（CKEST）延迟的中间时钟信号（CKINT1）的输入缓冲器（4）; 以及接收中间时钟信号（CKINT1）并提供分配在非易失性存储器（10）内并与外部时钟信号（CKEST）基本相位的内部时钟信号（CKINT）的延迟锁定环路（12）。

    Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit
    10.
    发明公开
    Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit 有权
    读取用于与突发读操作的自动检测非易失性存储器件的方法和相应的读出电路

    公开(公告)号：EP1103977A1

    公开(公告)日：2001-05-30

    申请号：EP99830722.7

    申请日：1999-11-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Geraci, Antonino ,  Sali, Mauro ,  Bedarida, Lorenzo

    IPC: G11C7/00

    CPC classification number: G11C7/1033 ,  G11C7/1045 ,  G11C7/1072

    Abstract: This invention relates to a method and a corresponding circuit for reading data from an integrated electronic memory device (2) including at least one non-volatile memory matrix (4). The method comprises the following steps:

    supplying the memory with an address of a memory location where a reading is to be effected;
    accessing the memory matrix in a random read mode;
    supplying the memory with a clock signal (CK) and an address acknowledge signal (LAN);
    detecting a request for burst read mode access;
    starting the burst reading as the clock signal shows a rising edge.

    Abstract translation: 本发明涉及一种方法和用于从上集成电子存储器装置（2）包括至少一个非易失性存储器矩阵中读取数据的相应的电路（4）。 该方法包括以下步骤：供给所述memoryWith到的存储器位置，其中的读出将要进行的地址; 访问在一个随机读取模式的存储器矩阵; 与时钟信号（CK）供给存储器，并处理确认信号（LAN）; 检测装置，用于突发读取模式访问的请求; 开始突发读出作为时钟信号示出了上升沿。

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