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    Nonvolatile memory device with multiple references and corresponding control method
    2.
    发明公开
    Nonvolatile memory device with multiple references and corresponding control method 有权
    NichtflüchtigerHalbleiterspeicher mit Referenzzellen und entspechendes Steuerverfahren

    公开(公告)号：EP1750281A1

    公开(公告)日：2007-02-07

    申请号：EP05425564.1

    申请日：2005-07-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bolandrina, Efrem ,  Vimercati, Daniele ,  Villa, Corrado

    IPC: G11C16/28 ,  G11C11/56

    CPC classification number: G11C11/5642 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634

    Abstract: A memory device includes a group (11, 17) of memory cells (12) organized in rows and columns and a first addressing circuit (14, 15) for addressing said memory cells (12) of said group (11, 17) on the basis of a cell address (ADD, AWL, ABL). The device further includes a plurality of sets of reference cells (19, 24), associated to the group (11, 17), each of said set having a plurality of reference cells (25a-25c, 26a-26c, 27, 28), and a second addressing circuit (20, 21) for addressing one of the reference cells (25a-25c, 26a-26c, 27, 28) during operations of read and verify of addressed memory cells (12).

    Abstract translation: 存储器件包括以行和列组织的存储器单元（12）的组（11,17）和用于对所述组（11,17）的所述存储器单元（12）进行寻址的第一寻址电路（14,15） 单元地址（ADD，AWL，ABL）的基础。 所述装置还包括与所述组（11,17）相关联的多组参考单元（19,24），所述组中的每一组具有多个参考单元（25a-25c，26a-26c，27,28） 以及用于在寻址和验证寻址的存储器单元（12）的操作期间寻址参考单元（25a-25c，26a-26c，27,28）之一的第二寻址电路（20,21）。

    A redundancy scheme for an integrated memory circuit
    3.
    发明公开
    A redundancy scheme for an integrated memory circuit 有权
    Redundanzschemafüreinen integrierten Speicherbaustein

    公开(公告)号：EP1498906A1

    公开(公告)日：2005-01-19

    申请号：EP03077228.9

    申请日：2003-07-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Martinelli, Andrea ,  Balluchi, Daniele ,  Villa, Corrado

    IPC: G11C29/00

    CPC classification number: G11C29/83

    Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors (S1-Sn) and, associated with each memory sector, a respective memory location selector (1031-103n) for selecting memory locations within the memory sector according to an address (ADD). The redundancy scheme comprises at least one redundant memory sector (RS1-RSm) adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry (111) for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means (1131-113n) are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line (VXR). A memory sector unusable status indicator element (211) is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

    Abstract translation: 一种用于具有至少两个存储器扇区（S1-Sn）并且与每个存储器扇区相关联的存储器集成电路的冗余方案，用于根据地址来选择存储器扇区内的存储器位置的相应存储器位置选择器（1031-103n） 加）。 所述冗余方案包括适于功能地替代所述至少两个存储器扇区中的一个的至少一个冗余存储器扇区（RS1-RSm），以及冗余控制电路（111），用于使被声明为不可用的存储器扇区的功能替换 所述至少一个冗余存储器扇区中的一个; 冗余控制电路检测对不可用存储器扇区内的存储器位置的访问请求，并将访问请求转发到冗余存储器扇区中的相应冗余存储器位置。 与每个存储器位置选择器相关联，提供相应的电源控制装置（1131-113n），其适于选择性地将相关联的存储器位置选择器连接/断开与电源分配线（VXR）的连接/断开。 存储器扇区不可用状态指示器元件（211）与每个存储器扇区相关联，用于控制相应的电源控制装置，以便在设置时引起各个存储器位置选择器与电源分配线的选择性断开。

    Synchronous-reading nonvolatile memory
    4.
    发明公开
    Synchronous-reading nonvolatile memory 审中-公开
    NichtflüchtigerSpeicher mit同步Lesemodus

    公开(公告)号：EP1225597A1

    公开(公告)日：2002-07-24

    申请号：EP01830016.0

    申请日：2001-01-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frulio, Massimiliano ,  Villa, Corrado ,  Bartoli, Simone

    IPC: G11C16/32 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/32

    Abstract: Described herein is a nonvolatile memory (10) comprising an input pin (2) receiving an external clock signal (CK EST ) supplied by a user; an input buffer (4) receiving the external clock signal (CK EST ) and supplying an intermediate clock signal (CK INT1 ) delayed with respect to the external clock signal (CK EST ); and a delay locked loop (12) receiving the intermediate clock signal (CK INT1 ) and supplying an internal clock signal (CK INT ) distributed within the nonvolatile memory (10) and substantially in phase with the external clock signal (CK EST ).

    Abstract translation: 这里描述的是一种非易失性存储器（10），包括接收由用户提供的外部时钟信号（CKEST）的输入引脚（2） 接收外部时钟信号（CKEST）并提供相对于外部时钟信号（CKEST）延迟的中间时钟信号（CKINT1）的输入缓冲器（4）; 以及接收中间时钟信号（CKINT1）并提供分配在非易失性存储器（10）内并与外部时钟信号（CKEST）基本相位的内部时钟信号（CKINT）的延迟锁定环路（12）。

    Electrically erasable and programmable non-volatile memory device with testable redundancy circuits
    5.
    发明授权
    Electrically erasable and programmable non-volatile memory device with testable redundancy circuits 失效
    与可测试冗余电路电可擦除和可编程的非易失性存储器设备

    公开(公告)号：EP0806773B1

    公开(公告)日：2003-03-19

    申请号：EP96830267.9

    申请日：1996-05-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dallabora, Marco ,  Villa, Corrado ,  Defendi, Marco

    IPC: G11C29/00

    CPC classification number: G11C29/24 ,  G11C29/02 ,  G11C29/44 ,  G11C29/824

    Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector (S1-S8) comprising an array of memory cells (MC) arranged in rows (WL0-WL255) and first-level columns (BL0-BL255), the first-level columns (BL0-BL255) being grouped together in groups of first-level columns each coupled to a respective second-level column (B1-B64), first-level selection means (2) for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means (3,4) for selecting one of the second-level columns, first direct memory access test means (SW6) activatable in a first test mode for directly coupling a selected memory cell (MC) of the array to a respective output terminal (Oi) of the memory device, redundancy columns (RBL0-RBL3) of redundancy memory cells (RMC) for replacing defective columns (BL0-BL255) of memory cells (MC), and a redundancy control circuit (CAM1-CAM4,5-7,12,SW1-SW5,24) comprising defective-address storage means (CAM1-CAM4) for storing addresses of the defective columns (BL0-BL255) and activating respective redundancy columns (RBL0-RBL3) when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means (24) activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements (AB0-AB7,GB) of the defective-address storage means (CAM1-CAM4) to respective second-level columns (B1-B64) of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals (Oi) of the memory device.

    Reduction of the time for executing an externally commanded transfer of data in an integrated device
    9.
    发明公开
    Reduction of the time for executing an externally commanded transfer of data in an integrated device 审中-公开
    在外部控制的数据传输的执行时间减小的集成器件

    公开(公告)号：EP1835618A1

    公开(公告)日：2007-09-19

    申请号：EP06425173.9

    申请日：2006-03-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Villa, Corrado ,  Zambelli, Yuri

    IPC: H03K5/15 ,  G06F1/10

    CPC classification number: H03K5/15013

    Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to a plurality of synchronizing and/or enabling circuits for performing a transfer of data to and from an integrated device, can be significantly reduced by having the external signal applied on a pad distributed unbuffered through a metal line of sufficiently large size (conductivity) such to introduce a negligible intrinsic propagation delay, though fulfilling the specified maximum admitted input pad capacitance, and by realizing locally dedicated input buffers to each of a plurality of synchronizing and/or enabling circuits of data transfer of the integrated device for applying thereto a buffered replica of the external signal present on said distributing metal line.

    Abstract translation: 通过在INPUTBUFFER和由含金属的引入累积延迟的贡献没有分配缓冲的外部控制信号，以同步和/或使能电路在集成设备执行传输数据的向和从的复数，可以显着地由具有减少的 应用上的焊盘的外部信号通过寻求以引入可忽略的固有传播延迟足够大的尺寸（导电率）的金属线分布缓冲，虽然满足规定的最大承认输入衬垫电容，并且通过实现本地专用输入缓冲器的每一个的多个 的同步和/或使该集成器件的数据传送电路，用于向其施加存在于所述分配含金属的外部信号的缓冲的复制品。

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