公开(公告)号：EP0936628A1

公开(公告)日：1999-08-18

申请号：EP98830066.1

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C16/24

Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to compare a voltage relating to a memory cell current, flowing in a bitline of a memory cell, to a reference voltage, by means of the use of an amplifying means, comprising bias means apt to define a bias voltage on the bitline for the sensing operation. According to the invention, there are provided further quick biasing means (C2) of the bitline (BL), apt to cooperate with said bias means (CB) in defining the bias voltage (VBL) of the bitline (BL), supplying a current substantially greater than the memory cell current (ICELL), in reply to a disabling signal (DIS), said quick biasing means (C2) being also apt to disable itself before the said bias voltage (VBL) is reached.

Abstract translation: 用于非易失性存储器的感测放大器电路，其类型是借助于使用放大装置将与在存储器单元的位线中流动的存储器单元电流相关的电压与参考电压相比较的类型，包括偏置 意味着可以在位线上定义感测操作的偏置电压。 根据本发明，提供了位线（BL）的进一步的快速偏置装置（C2），在定义位线（BL）的偏置电压（VBL）时易于与所述偏置装置（CB）配合，提供电流 基本上大于存储单元电流（ICELL），响应于禁用信号（DIS），所述快速偏置装置（C2）在达到所述偏置电压（VBL）之前也易于自身失效。

公开(公告)号：EP0936620A1

公开(公告)日：1999-08-18

申请号：EP98830065.3

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Demange, Nicolas ,  Gaibotti, Maurizio

IPC: G11C7/00 ,  G11C16/06

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: Biasing system of a bitline in a sense circuit for a non-volatile wide supply voltage range memory, in particular an EEPROM type memory, comprising an amplifier with two inputs to which two current sensing branches are connected, one current being relative to the memory cell and the other one taken from a reference circuit, of the type using a transistor for defining a biasing voltage onto a bitline, said transistor being biased through a voltage obtained by means of a feedback circuit connected to the relevant bitline. According to the invention, in order to supply the said biasing voltage (VBL), said transistor (N1) is in turn biased by a voltage (VGN1), which is in turn obtained through a circuit wherein a stable current (IP) flows, independent from the supply voltage (VDD) value, so that said biasing voltage (VBL) is independent from the supply voltage (VDD) value.

Abstract translation: 偏置位线的系统中的感测电路用于非易失性宽电源电压范围内存，尤其是EEPROM型存储器，具有两个输入到哪两个电流感测支路被连接时，电流相对于存储器单元之一是放大器，其包括 和来自参考电路所使用限定的偏置电压施加到位线的晶体管的类型，另一种，所述晶体管被通过连接到相关位线的反馈电路而获得的电压偏置。 。根据本发明，为了提供所述偏压电压（VBL），所述晶体管（N1）又由一电压（VGN1）施力，所有这些又通过worin稳定的电流（IP）流过的电路获得， 独立于电源电压（VDD）的值，使得所述偏置电压（VBL）是独立于电源电压（VDD）的值。

公开(公告)号：EP1653315A1

公开(公告)日：2006-05-03

申请号：EP04105351.3

申请日：2004-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Pisasale, Michelangelo ,  Gaibotti, Maurizio ,  La Placa, Michele

IPC: G05F1/46 ,  G11C5/14 ,  G05F3/26

CPC classification number: G05F3/262 ,  G11C5/147

Abstract: A voltage down converter (200) includes voltage regulator means (205) receiving a first voltage (Vdd) and having a regulation node for providing a regulated second voltage (Vr) lower than the first voltage, and having a control node for providing a control voltage (Vg) corresponding to the second voltage; and a voltage driver circuit branch (220) receiving the first voltage and including a variable-conductivity element (Tsb) having a control terminal coupled to the control node for controlling a current sunk by the variable-conductivity element from the first voltage; The voltage driver circuit branch has a voltage supply node (Vo), for supplying a down-converted voltage (Vo) corresponding to the second voltage, which is decoupled from the regulation node. At least one additional voltage driver circuit branch (225-1 - 225-N) is provided, receiving the first voltage and coupled to the voltage supply node, and including: a further variable-conductivity element (T-1 - T-N) having a control terminal coupled to the control node for controlling a current sunk by the further variable-conductivity element from the first voltage; and switching means (SW-1 - SW-N) for selectively enabling the further variable-conductivity element so as to keep the down-converted voltage at a prescribed value depending on the regulated second voltage.

Abstract translation: 降压转换器（200）包括接收第一电压（Vdd）并具有用于提供低于第一电压的调节的第二电压（Vr）的调节节点的电压调节器装置（205），并具有用于提供控制的控制节点 对应于第二电压的电压（Vg）; 以及电压驱动电路分支（220），其接收所述第一电压并且包括具有耦合到所述控制节点的控制端的可变导电性元件（Tsb），用于控制由所述可变电导率元件从所述第一电压引起的电流下降; 电压驱动器电路分支具有电压供应节点（Vo），用于提供与调节节点分离的对应于第二电压的下变频电压（Vo）。 提供至少一个额外的电压驱动器电路分支（225-1-225-N），接收第一电压并耦合到电压供应节点，并且包括：另一可变导电元件（T-1-TN），其具有 控制端子，其耦合到所述控制节点，用于通过所述另一可变电导率元件从所述第一电压控制当前的下沉; 以及切换装置（SW-1-SW-N），用于选择性地使能另外的可变导电性元件，以便根据调节的第二电压将下变频电压保持在规定值。

公开(公告)号：EP0936627B1

公开(公告)日：2004-10-20

申请号：EP98830064.6

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06 ,  G11C7/06

CPC classification number: G11C16/24 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28

公开(公告)号：EP1220448A1

公开(公告)日：2002-07-03

申请号：EP01130836.8

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Zerilli, Tommaso ,  Gaibotti, Maurizio

IPC: H03K4/502

CPC classification number: H03K4/00 ,  H03K17/163

Abstract: The present invention refers to a generator circuit (3) for voltage ramps having an improved dynamic operation of the type comprising a differential stage (4) of a first output which controls a p-channel transistor (M1). A positive feedback branch is provided between the drain of the p-channel transistor (M1) and a first input of the differential stage and comprises a capacitor (C1). A current generator (G1) provides current to the first input of the differential stage. The drain of the p-channel transistor (M1) is also connected at an output terminal (OUT) of said ramp generator circuit (3) to a capacitative charge (C1) to be biased with voltage ramps.
Advantageously, the ramp generator circuit comprises a second n-channel output transistor (N3) parallel connected to said p-channel transistor (P3) and having the control terminal connected to a second output (X1) of said differential stage (4).

Abstract translation: 本发明涉及一种用于电压斜坡的发生器电路（3），其具有改进的动态操作，其类型包括控制p沟道晶体管（M1）的第一输出的差分级（4）。 在p沟道晶体管（M1）的漏极和差分级的第一输入端之间提供正反馈支路，并且包括电容器（C1）。 电流发生器（G1）向差动级的第一输入提供电流。 p沟道晶体管（M1）的漏极也在所述斜坡发生器电路（3）的输出端（OUT）连接到电容性电荷（C1）以被电压斜坡偏置。 有利地，斜坡发生器电路包括并联连接到所述p沟道晶体管（P3）并使控制端子连接到所述差分级（4）的第二输出（X1）的第二n沟道输出晶体管（N3）。

公开(公告)号：EP1220448B1

公开(公告)日：2004-03-03

申请号：EP01130836.8

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Zerilli, Tommaso ,  Gaibotti, Maurizio

IPC: H03K4/502

CPC classification number: H03K4/00 ,  H03K17/163

公开(公告)号：EP0768758B1

公开(公告)日：2004-01-02

申请号：EP95830430.5

申请日：1995-10-12

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Adduci, Francesco

IPC: H03K3/3562

CPC classification number: H03K3/35625

公开(公告)号：EP0936627A1

公开(公告)日：1999-08-18

申请号：EP98830064.6

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06 ,  G11C7/06

CPC classification number: G11C16/24 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28

Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current from a reference bitline and a cell current from a cell array bitline, and compare them by means of current-voltage converting means and an amplifying stage, said current-voltage converting means comprising also fixing means of a determined voltage on the reference bitline and on the cell array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror circuits for mirroring the reference current into a input node of the amplifying stage and the cell current into a further input of said amplifying stage. According to the invention the load circuit means of the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different circuits and the reference bitline load circuit means are represented by a transistor (P3) which mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order to have a lower voltage drop on said load circuit means (P3).

Abstract translation: 用于非易失性存储器的感测放大器电路，其类型适于从参考位线绘制参考电流，并从单元阵列位线画出单元电流，并且通过电流 - 电压转换装置和放大级比较它们，所述电流 - 电压转换装置，还包括在参考位线和单元阵列位线上的确定电压的固定装置，用于参考位线和单元阵列位线的负载电路装置，用于将参考电流镜像到输入节点的电流镜电路 放大级和电池电流进入所述放大级的另一输入。 根据本发明，参考电位线（BLREF）和参考电流的镜像装置（MR）的负载电路装置是不同的电路，参考位线负载电路装置由反映预定电流的晶体管（P3）表示 IP），以在所述负载电路装置（P3）上具有较低的电压降。