公开(公告)号：EP0936627A1

公开(公告)日：1999-08-18

申请号：EP98830064.6

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06 ,  G11C7/06

CPC classification number: G11C16/24 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28

Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current from a reference bitline and a cell current from a cell array bitline, and compare them by means of current-voltage converting means and an amplifying stage, said current-voltage converting means comprising also fixing means of a determined voltage on the reference bitline and on the cell array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror circuits for mirroring the reference current into a input node of the amplifying stage and the cell current into a further input of said amplifying stage. According to the invention the load circuit means of the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different circuits and the reference bitline load circuit means are represented by a transistor (P3) which mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order to have a lower voltage drop on said load circuit means (P3).

Abstract translation: 用于非易失性存储器的感测放大器电路，其类型适于从参考位线绘制参考电流，并从单元阵列位线画出单元电流，并且通过电流 - 电压转换装置和放大级比较它们，所述电流 - 电压转换装置，还包括在参考位线和单元阵列位线上的确定电压的固定装置，用于参考位线和单元阵列位线的负载电路装置，用于将参考电流镜像到输入节点的电流镜电路 放大级和电池电流进入所述放大级的另一输入。 根据本发明，参考电位线（BLREF）和参考电流的镜像装置（MR）的负载电路装置是不同的电路，参考位线负载电路装置由反映预定电流的晶体管（P3）表示 IP），以在所述负载电路装置（P3）上具有较低的电压降。

公开(公告)号：EP0936627B1

公开(公告)日：2004-10-20

申请号：EP98830064.6

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06 ,  G11C7/06

CPC classification number: G11C16/24 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28

公开(公告)号：EP1306851A1

公开(公告)日：2003-05-02

申请号：EP01830667.0

申请日：2001-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Torrisi, Salvatore ,  Siberno, Giampiero ,  Demange, Nicolas

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A method of sensing a ferroelectric non-volatile information storage units ( 103 ) comprising two ferroelectric storage capacitors ( Cc,Ct ) in mutually opposite polarization states, and a sensing circuit for actuating the method. The method comprises the steps of: making a voltage applied across the two storage capacitors substantially zero ( Ph1 ); starting from this condition, progressively increasing the voltage applied thereacross ( Ph2 ) by supplying a prescribed current, until a first one ( Ct ) of the two storage capacitors approaches a condition of polarization state reversal, thereby the voltage applied across said first storage capacitor starts to decrease with respect to the voltage applied across the second storage capacitor ( Cc ); and amplifying a voltage difference between the voltages applied across the two storage capacitors by making the voltage applied across the first storage capacitor substantially zero and the voltage applied across the second storage capacitor substantially equal to a non-zero voltage ( VDD ) corresponding to a logic state opposite to a logic state corresponding to the zero voltage.

Abstract translation: 感测铁电非易失性信息存储单元（103）在相互相反的偏振态包括两个铁电存储电容器（CC，CT）的方法，和用于致动方法的感测电路。 该方法包括如下步骤：使得在所述两个辅助电容基本为零（PH1）施加的电压; 从该状态开始，通过供给规定的电流逐渐增大的电压施加通过（Ph2的），直到两个存储电容器中的第一个（CT）途径偏振状态反转的状态，从而横跨所述第一存储电容器开始施加的电压 相对于横过所述第二存储电容器（CC）施加的电压降低; 并且通过使对应于逻辑跨第一存储电容器基本上为零和跨过第二存储电容器基本上等于一个非零电压（VDD）施加的电压施加的电压放大跨越两个存储电容器上的电压应用之间的电压差 状态相反逻辑状态对应于零电压。

公开(公告)号：EP1304701A1

公开(公告)日：2003-04-23

申请号：EP01830656.3

申请日：2001-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Demange, Nicolas ,  Torrisi, Salvatore ,  Sberno, Giampiero

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit (103,403) comprises a pre-charge circuit (113;413t,413c) for applying a prescribed pre-charge voltage (Vprch) to a storage capacitor (C;Ct,Cc) of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit (115,CAP;115t,115c,CAPt,CAPc) is provided for integrating an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage (Voutsw,Voutln) depending on the polarization state of the storage capacitor. The charge integration circuit may comprises an integration capacitor (CAP;CAPt,CAPc) and current mirror circuit (115;415t,415c) , with a first mirror branch (115a) coupled to the pre-charge circuit and a second mirror branch (115b) coupled to the integration capacitor, for mirroring into the second mirror branch an electric charge (Qsw,Qln) supplied to the information storage unit to compensate for the variation in the polarization charge experienced by the storage capacitor.

Abstract translation: 用于感测铁电非易失性信息存储单元（103,403）的电路包括用于将规定的预充电电压（Vprch）施加到存储电容器（C; Ct，Cc）的预充电电路（113; 413t，413c） 的信息存储单元。 根据存储电容器的初始极化状态，预充电电压导致存储电容器的极化电荷的变化。 提供电荷积分电路（115，CAP; 115t，115c，CAPt，CAPc）用于积分与存储电容器经历的极化电荷的变化成比例的电荷。 因此，电荷积分电路根据存储电容器的极化状态提供输出电压（Voutsw，Voutln）。 电荷积分电路可以包括积分电容器（CAP; CAPt，CAPc）和电流镜电路（115; 415t，415c），其中耦合到预充电电路的第一反射镜分支（115a）和第二反射镜分支（115b ）耦合到积分电容器，用于将提供给信息存储单元的电荷（Qsw，Qln）镜像到第二镜像分支中，以补偿存储电容器经历的极化电荷的变化。

公开(公告)号：EP0936628A1

公开(公告)日：1999-08-18

申请号：EP98830066.1

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Gaibotti, Maurizio ,  Demange, Nicolas

IPC: G11C16/06

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C16/24

Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to compare a voltage relating to a memory cell current, flowing in a bitline of a memory cell, to a reference voltage, by means of the use of an amplifying means, comprising bias means apt to define a bias voltage on the bitline for the sensing operation. According to the invention, there are provided further quick biasing means (C2) of the bitline (BL), apt to cooperate with said bias means (CB) in defining the bias voltage (VBL) of the bitline (BL), supplying a current substantially greater than the memory cell current (ICELL), in reply to a disabling signal (DIS), said quick biasing means (C2) being also apt to disable itself before the said bias voltage (VBL) is reached.

Abstract translation: 用于非易失性存储器的感测放大器电路，其类型是借助于使用放大装置将与在存储器单元的位线中流动的存储器单元电流相关的电压与参考电压相比较的类型，包括偏置 意味着可以在位线上定义感测操作的偏置电压。 根据本发明，提供了位线（BL）的进一步的快速偏置装置（C2），在定义位线（BL）的偏置电压（VBL）时易于与所述偏置装置（CB）配合，提供电流 基本上大于存储单元电流（ICELL），响应于禁用信号（DIS），所述快速偏置装置（C2）在达到所述偏置电压（VBL）之前也易于自身失效。

公开(公告)号：EP1566809B1

公开(公告)日：2006-11-29

申请号：EP04290449.0

申请日：2004-02-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

Inventor： Demange, Nicolas ,  Conte, Antonino ,  Preciso, Salvatore ,  Signorello, Alfredo

IPC: G11C7/14 ,  G11C7/10

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

公开(公告)号：EP0936621B1

公开(公告)日：2006-04-26

申请号：EP98830067.9

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Demange, Nicolas

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C7/067 ,  G11C16/26

公开(公告)号：EP1566809A1

公开(公告)日：2005-08-24

申请号：EP04290449.0

申请日：2004-02-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

Inventor： Demange, Nicolas ,  Conte, Antonino ,  Preciso, Salvatore ,  Signorello, Alfredo

IPC: G11C7/14 ,  G11C7/10

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.

Abstract translation: 一种用于感测电流的感测电路（120），包括至少一个读出放大器（122），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于转换输入 电流进入相应的输入电压（V-）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 和用于比较输入和比较电压的至少一个电压比较器（140）和用于基于参考电流（Ir）产生比较电流的装置（N3s，135; N3s，135'; N3s，135“）， 包括：用于接收所述参考电流并用于产生相应的读出放大器偏置电压（Vsab）的至少一个电压发生器（135; 135'; 135“）;以及用于将所述读出放大器偏置电压转换成比较的装置（N3s） 所述至少一个电压发生器包括第一电路分支（232i），其具有用于接收所述参考电流的第一节点，用于将所述参考电流转换为对应的参考电压（Vref）;第二电路分支（232o），具有 用于以电流镜配置接收调节电流（Ii）的第二节点，其中第一电路支路用于镜像对应于参考电流的电流（Img），第二电路支路通过转换产生非调节电压（ Vgen）和调节电流相对应的电压调节器装置（N3g，240）以及通过调节电流控制非调节电压来调节读出放大器偏置电压的非调节电压 。

公开(公告)号：EP0936621A1

公开(公告)日：1999-08-18

申请号：EP98830067.9

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Demange, Nicolas

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C7/067 ,  G11C16/26

Abstract: Memory sense amplifier, specifically EEPROM memories, operating in an extended supply voltage range, comprising a comparator that on an input receives a signal available on a bit line representative of the current flowing through the read memory cell and on another input it receives a signal representative of a reference current available on another bit line, and a bit lines polarization system.
According to this invention the comparator comprises a stage in common source configuration (N2) and an active load (P5) for said stage.
Moreover, the bit lines polarization system releases a polarization value (VBL) independent from the supply voltage value (VDD).

Abstract translation: 存储器读出放大器，特别是EEPROM存储器，在扩展电源电压范围内操作的方法，包括一个比较器做了在输入端接收表示所述电流的位线流过读取存储单元并在另一个输入提供的信号接收到的信号代表 另一个位线提供参考电流，和一个位线的偏振系统。。根据本发明中的比较器包括在共用源极配置（N 2）和到有源负载（P5）用于所述阶段的阶段。 更上方，位线偏振系统释放独立于电源电压值（VDD）的偏振值（VBL）。

公开(公告)号：EP0936620A1

公开(公告)日：1999-08-18

申请号：EP98830065.3

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Demange, Nicolas ,  Gaibotti, Maurizio

IPC: G11C7/00 ,  G11C16/06

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: Biasing system of a bitline in a sense circuit for a non-volatile wide supply voltage range memory, in particular an EEPROM type memory, comprising an amplifier with two inputs to which two current sensing branches are connected, one current being relative to the memory cell and the other one taken from a reference circuit, of the type using a transistor for defining a biasing voltage onto a bitline, said transistor being biased through a voltage obtained by means of a feedback circuit connected to the relevant bitline. According to the invention, in order to supply the said biasing voltage (VBL), said transistor (N1) is in turn biased by a voltage (VGN1), which is in turn obtained through a circuit wherein a stable current (IP) flows, independent from the supply voltage (VDD) value, so that said biasing voltage (VBL) is independent from the supply voltage (VDD) value.

Abstract translation: 偏置位线的系统中的感测电路用于非易失性宽电源电压范围内存，尤其是EEPROM型存储器，具有两个输入到哪两个电流感测支路被连接时，电流相对于存储器单元之一是放大器，其包括 和来自参考电路所使用限定的偏置电压施加到位线的晶体管的类型，另一种，所述晶体管被通过连接到相关位线的反馈电路而获得的电压偏置。 。根据本发明，为了提供所述偏压电压（VBL），所述晶体管（N1）又由一电压（VGN1）施力，所有这些又通过worin稳定的电流（IP）流过的电路获得， 独立于电源电压（VDD）的值，使得所述偏置电压（VBL）是独立于电源电压（VDD）的值。