公开(公告)号：EP4131364A3

公开(公告)日：2023-06-14

申请号：EP22188099.0

申请日：2022-08-01

Applicant: STMicroelectronics S.r.l.

Inventor： MARIANI, Simone Dario ,  PIZZI, Elisabetta ,  DORIA, Daria

IPC: H01L23/31 ,  H01L21/60 ,  H01L23/522

Abstract: A back end of line (BEOL) structure for an integrated circuit chip (10) includes a last metal structure (20, 32) providing a bonding pad (20). A passivation structure (28o)ver the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer (42) extends over the passivation structure and is placed in contact with the upper surface of the bonding pad (32, 20). An insulator material layer (50) covers the conformal nitride layer (42) and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

公开(公告)号：EP4131364A2

公开(公告)日：2023-02-08

申请号：EP22188099.0

申请日：2022-08-01

Applicant: STMicroelectronics S.r.l.

Inventor： MARIANI, Simone Dario ,  PIZZI, Elisabetta ,  DORIA, Daria

IPC: H01L23/31 ,  H01L21/60 ,  H01L23/522

Abstract: A back end of line (BEOL) structure for an integrated circuit chip (10) includes a last metal structure (20, 32) providing a bonding pad (20). A passivation structure (28o)ver the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer (42) extends over the passivation structure and is placed in contact with the upper surface of the bonding pad (32, 20). An insulator material layer (50) covers the conformal nitride layer (42) and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

公开(公告)号：EP3511988A1

公开(公告)日：2019-07-17

申请号：EP19151957.8

申请日：2019-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： PATTI, Davide Giuseppe ,  SAMBI, Marco ,  TOIA, Fabrizio Fausto Renzo ,  MARIANI, Simone Dario ,  PIZZI, Elisabetta ,  BARILLARO, Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L21/02

Abstract: A vertical-conduction semiconductor electronic device (40, comprising: a semiconductor body (1, 2); a body region (30) in the semiconductor body (1, 2); a source terminal (32) in the body region (30); a drain terminal (38) spatially opposite to the source region; and a trench gate (6, 14, 16', 24) extending in depth in the semiconductor body through the body region (30) and the source region (32). The trench gate includes a dielectric region (14) of porous silicon oxide buried in the semiconductor body, and a gate conductive region (24) extending between the dielectric region (14) of porous silicon oxide and said first side (2a).