公开(公告)号：WO2011079883A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005932

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICOTTI, Giulio

Inventor： ROSSI, Sandro ,  RICOTTI, Giulio

IPC: H03K17/0416 ,  H03K17/16 ,  H03K17/74 ,  B06B1/02

CPC classification number: H03K17/74 ,  B06B1/0215 ,  H03K17/04163 ,  H03K17/161

Abstract: A transmission channel (1) is described of the type comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1, HVMO, HVM1), these buffer transistors (MB1, MB2, MB3, MB4) being also connected to a clamping block (5), in turn comprising clamping transistors (MC1, MC2) connected to at least one output terminal (HVout) of this transmission channel through diodes (DC1, DC2) connected to prevent the body diodes of the clamping transistors (MC1, MC2) from conducting. Advantageously according to the invention, the transmission channel (1) comprises at least one reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping block (5), these circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) being in correspondence with conduction terminals of the transistors (MB l, MB2, MB3, MB4; MC1, MC2) comprised into the high voltage buffer block (4) and into the clamping block (5).

Abstract translation: 描述了包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4）的传输通道（1） 在相应的电压基准（HVPO，HVP1，HVMO，HVM1）之间，这些缓冲晶体管（MB1，MB2，MB3，MB4）也连接到钳位块（5），反过来又包括钳位晶体管（MC1，MC2） 所述传输通道的至少一个输出端子（HVout）通过连接的二极管（DC1，DC2），以防止钳位晶体管（MC1，MC2）的体二极管导通。 有利地，根据本发明，传输通道（1）包括至少一个包括二极管（DME1，DME2，DME3，DME4）的复位电路（20），并且插入在电路节点（XME1，XME2，XME3，XME4，XC1，XC2 ）和高压缓冲块（4）和钳位块（5）的这些电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与晶体管（MB1，MB2， MB3，MB4; MC1，MC2）组成高压缓冲块（4）并进入夹紧块（5）。

公开(公告)号：WO2011079882A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005931

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

Inventor： ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

IPC: H03K17/0416 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  B06B1/02

CPC classification number: H03K17/063 ,  B06B1/0215 ,  H03K17/04163 ,  H03K17/162 ,  H03K17/6872

Abstract: A switching circuit (30) is described being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between the connection terminal (Xdcr) and the output terminal (LVout). Advantageously according to the invention, the switching circuit comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG1, XG2) of these at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between these first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB1, XB2) of at least one order of magnitude lower with respect to the gate-source capacities (Csw1, Csw2) of these at least one first and one second switching transistor (MSW1, MSW2).

Abstract translation: 描述了切换电路（30）被插入在传输通道（1）的连接端子（Xdcr）和输出端子（LVout）之间，并且包括至少一个第一和第二开关晶体管（MSW1，MSW2）的类型， （Xdcr）和输出端子（LVout）之间具有反相串联的相应的等效或体二极管（DSW1，DSW2）。 有利地，根据本发明，切换电路包括连接到这些至少一个第一和第二开关晶体管（MSW1，MSW2）的相应的第一和第二控制端子（XG1，XG2）的至少一个自举电路（31），以及 对于相应的第一和第二参考电压（VDD_P，VDD_M），并且具有这些第一和第二控制端子（XG1，XG2）之间的寄生电容值和至少一个第一和第二引导节点（XB1，XB2） 相对于这些至少一个第一和第二开关晶体管（MSW1，MSW2）的栅极 - 源极电容（Csw1，Csw2）的数量级下降。

公开(公告)号：WO2011063974A1

公开(公告)日：2011-06-03

申请号：PCT/EP2010/007185

申请日：2010-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  ROSSI, Sandro

IPC: H03K3/355

CPC classification number: H03K3/355

Abstract: It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first portion (2A) connected to a first voltage reference (VPH) and including at least one first output transistor (MOP) being inserted between the first voltage reference (VPH) and the output terminal (OUT), such a first portion (2A) further comprising: at least one first high voltage comparator (3A) being connected to said output terminal (OUT) and to a first threshold voltage reference (VTHP), at least one first start-up circuit (4A) being controlled by a first setting signal (SETP); at least one first switching ON /OFF circuit (5A) being connected at its input to the first start-up circuit (4A), in correspondence with a first internal circuit node (XP), and to the first high voltage comparator (3A), in correspondence with a second internal circuit node (YP), and at its output to a control terminal of the first output transistor (MOP); the first start-up circuit (4A) providing a switching on signal (ONA) to the first switching on/ off circuit (5A) while the high voltage comparator (3A) provides a switching off signal (OFFA) to the first switching on/ off circuit (5A) which causes the switching off of the output transistor (MOP), the high voltage comparator (3A) generating the switching off signal (OFFA) when the output voltage (Vout) reaches a first desired supply voltage value which depends on the value of the first threshold voltage reference (VTHP).

Abstract translation: 描述了具有连接到超声波脉冲发生器电路并向其提供输出电压（Vout）的至少一个输出端子（OUT）的驱动电路（1），其特征在于它包括至少一个连接的第一部分（2A） 至少一个第一输出晶体管（MOP）被插入在第一参考电压（VPH）和输出端子（OUT）之间，所述第一部分（2A）还包括：至少一个 第一高压比较器（3A）连接到所述输出端（OUT）和第一阈值电压基准（VTHP），至少一个第一启动电路（4A）由第一设置信号（SETP）控制; 至少一个第一开关ON / OFF电路（5A）在其输入端与第一内部电路节点（XP）相对应地连接到第一启动电路（4A），并连接到第一高电压比较器（3A） 对应于第二内部电路节点（YP），并且在其输出端与第一输出晶体管（MOP）的控制端相对应; 所述第一启动电路（4A）向所述第一开关导通/断开电路（5A）提供开启信号（ONA），同时所述高电压比较器（3A）向所述第一开关导通/断开电路提供断开信号（OFFA） 关闭电路（5A），当输出电压（Vout）达到第一期望的电源电压值时，高电压比较器（3A）产生关断信号（OFFA），导致关闭输出晶体管（MOP） 第一阈值电压基准值（VTHP）。

公开(公告)号：WO2011088853A1

公开(公告)日：2011-07-28

申请号：PCT/EP2010/005927

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

Inventor： ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/74 ,  B06B1/02 ,  H03K17/0416 ,  H03K17/16

CPC classification number: H03K17/06 ,  H03K17/04163 ,  H03K17/161 ,  H03K17/6872 ,  H03K17/74

Abstract: A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).

Abstract translation: 描述了传输通道（1），其包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4） 参考（HVP0，HVP1，HVM0，HVM1），与传输通道（1）的第一输出端子（HVout）连接的钳位电路（10），连接在第一输出端子 ）和传输信道（1）的连接终端（Xdcr）; 以及插入在传输通道（1）的连接端子（Xdcr）和第二输出端子（LVout）之间的开关电路（30）。 有利地，根据本发明，夹紧电路（10）包括夹紧芯（11），复位电路（20），其包括插入在电路节点（XME1，XME2，XME3，XME4，XME3，DME3， 高电压缓冲块（4）和钳位电路（10）的电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与所述晶体管（MB1，XC1，XC2）的导通端子相对应， MB2，MB3，MB4，MC1，MC2）以及开关电路（30），其特征在于，包括高压缓冲块（4）和钳位电路（10）。

公开(公告)号：WO2011045083A1

公开(公告)日：2011-04-21

申请号：PCT/EP2010/006339

申请日：2010-10-18

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

IPC: H03K17/74

CPC classification number: H03K17/063

Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

Abstract translation: 本发明涉及一种具有接收输入信号（Vin）以驱动负载的输入端（IN）和向负载发出输出信号（Vout）的输出端（OUT）的高压开关配置（10）。 有利地，根据本发明，高压开关配置（10）至少包括第一和第二二极管（D1，D2），放置在所述输入和输出端子（IN，OUT）之间的反电容中，并具有一对相应的 端子，对应于第一内部电路节点（Xc1）。

公开(公告)号：WO2012077145A8

公开(公告)日：2012-06-14

申请号：PCT/IT2010/000493

申请日：2010-12-09

Applicant: STMICROELECTRONICS S.R.L. ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio ,  ROSSI, Sandro

Inventor： GHISU, Davide Ugo ,  RICCIARDO, Antonio ,  ROSSI, Sandro

IPC: B06B1/02 ,  H03K17/10 ,  H03K17/687 ,  H03K17/693

Abstract: A switching circuit (10) for an ultrasound transmission channel (1) is inserted between a connection terminal (Xdcr) and a low voltage output terminal (LVout) and comprising a receiving switch (30) a high voltage clamp circuit (HV1) inserted between the connection terminal (Xdcr) and a central node (Vc), a low voltage clamping switch (25) inserted between said central node (Vc) and a reference voltage (GND), the receiving switch (30) being low voltage and being inserted between the central node (Vc) and the low voltage output terminal (LVout), the clamping switch (25) and the receiving switch (30) being controlled in a complementary way with respect to each other. A transmission channel ( 1) for ultrasound applications is also described comprising at least such a switching circuit (10) and a process for driving said switching circuit (10).

公开(公告)号：WO2011079881A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005930

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio

Inventor： ROSSI, Sandro ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/74 ,  B06B1/02

CPC classification number: H03K17/6872 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/74

Abstract: A clamping circuit (10) to a voltage reference (GND) is described, of the type comprising at least one clamping core (11) connected to an output terminal (HVout) and having a central node (XC) connected to the voltage reference (GND) and in turn including at least one first and one second clamp transistor (MC1; MC2), connected to the central node (XC) and having respective control terminals (XG1, XG2), the clamping core (11) being also connected at the input to a low voltage input driver block (13). Advantageously according to the invention, the clamping core (11) further comprises at least one first switching off transistor (MS1) connected to the output terminal (HVout) and to the first clamp transistor (MC1), as well as a second switching off transistor (MS2) connected to the output terminal (HVout) and to the second clamp transistor (MC2), these first and second clamp transistors (MC1, MC2) being high voltage MOS transistors of complementary type and these first and second switching off transistors (MS1, MS2) being high voltage MOS transistors of complementary type and connected to the first and second clamp transistors (MC1, MC2) by having the respective equivalent or body diodes in anti-series so as to close themselves when the clamping circuit (10) is active and to sustain positive and negative high voltages when the clamping circuit (10) is not active.

Abstract translation: 描述了到电压基准（GND）的钳位电路（10），其类型包括连接到输出端子（HVout）的至少一个夹紧芯部（11），并且具有连接到电压基准的中心节点（XC） GND），并且还包括连接到中心节点（XC）并且具有各自的控制端子（XG1，XG2）的至少一个第一和第二钳位晶体管（MC1; MC2），夹紧芯部（11）也连接在 输入到低电压输入驱动器块（13）。 有利地，根据本发明，夹紧芯（11）还包括连接到输出端（HVout）和第一钳位晶体管（MC1）的至少一个第一截止晶体管（MS1）以及第二截止晶体管 （MC2）连接到输出端子（HVout）和第二钳位晶体管（MC2）的这些第一和第二钳位晶体管（MC1，MC2）是互补型高压MOS晶体管，这些第一和第二截止晶体管 ，MS2）是互补型的高电压MOS晶体管，通过使相应的等效或体二极管反串联以便在钳位电路（10）为 当钳位电路（10）未被激活时，它有效并维持正和负的高电压。

公开(公告)号：WO2011063873A1

公开(公告)日：2011-06-03

申请号：PCT/EP2010/005928

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ALBERTINI, Matteo ,  RONCHI, Daniele ,  ROSSI, Sandro ,  RICOTTI, Giulio

Inventor： ALBERTINI, Matteo ,  RONCHI, Daniele ,  ROSSI, Sandro ,  RICOTTI, Giulio

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03F3/45183 ,  H03F3/45098 ,  H03F2200/294 ,  H03F2200/453 ,  H03F2203/45492 ,  H03F2203/45674

Abstract: The invention relates to a driving method for obtaining a linear gain variation of a transconductance amplifier, of the type comprising at least one differential transistor cell, with adjustment of a driving voltage value (Vtgc1) of a degenerative driving transistor (MD1) of said transconductance amplifier, comprising the steps of : generating an output current signal of a differential cell (11) being a copy of said differential transistor cell of said transconductance amplifier, said output current signal having a linear relationship with a transconductance value of said copy differential cell (11) as said driving voltage (Vtgc1) varies; generating a reference current signal having a linear relationship with a differential input voltage; comparing said output current signal and said reference current signal for adjusting said driving voltage value (Vtgc1) and modifying said transconductance value of said copy differential cell (11) up to a balance of said current signals.

Abstract translation: 本发明涉及一种用于获得包括至少一个差分晶体管单元的类型的跨导放大器的线性增益变化的驱动方法，其中调节所述跨导的退化驱动晶体管（MD1）的驱动电压值（Vtgc1） 放大器，包括以下步骤：产生作为所述跨导放大器的所述差分晶体管单元的副本的差分单元（11）的输出电流信号，所述输出电流信号与所述复制差分单元的跨导值具有线性关系（ 11），因为所述驱动电压（Vtgc1）变化; 产生与差分输入电压具有线性关系的参考电流信号; 比较所述输出电流信号和所述参考电流信号，用于调节所述驱动电压值（Vtgc1），并修改所述复制差分单元（11）的所述跨导值直到所述电流信号的平衡。

公开(公告)号：EP2648858B1

公开(公告)日：2019-02-13

申请号：EP10807487.3

申请日：2010-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： GHISU, Davide Hugo ,  RICCIARDO, Antonio ,  ROSSI, Sandro

IPC: H03K17/693 ,  H03K5/08 ,  H03K17/10 ,  H03K17/687

公开(公告)号：EP3217551A1

公开(公告)日：2017-09-13

申请号：EP16190816.5

申请日：2016-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  BOTTAREL, Valeria

IPC: H03K17/0412 ,  H03K3/3565 ,  H03K19/0185 ,  H03K17/06 ,  H03K17/687

Abstract: Gate driver circuit for a half bridge or full bridge output driver stage, identifying a high side branch connected to one or more high side transistors (Mp) and a low side branch connected to one or more low side transistors (Mn), comprising
a high side gate driver (10; 21p) and a low side gate driver (10n; 21n) receiving input signals at a low voltage level (VDD) and operating with a high voltage level (VPP), outputting signals at a high voltage level as gate driving signals (Gp, Gn) for the high side transistors (Mp) and low side transistors (Mn)
In the solution described the high side and the low side branches of the gate driver (11) include each
a set-reset latch (24p, 24n) which signal output (Qp, Qpn) is fed as gate signal to the corresponding transistor (Mp, Mn) of the half bridge or full bridge driver (11),
a differential capacitive level shifter circuit (23p, 23n) receiving said input signals at a low voltage level and outputting high voltage signals to drive the set (S) and reset (R) inputs of the set-reset latch (24p, 24n).

Abstract translation: 用于半桥或全桥输出驱动级的栅极驱动器电路，识别连接到一个或多个高侧晶体管（Mp）的高侧分支和连接到一个或多个低侧晶体管（Mn）的低侧分支，所述栅极驱动器电路包括高 接收低电压电平（VDD）的输入信号并以高电压电平（VPP）工作的高侧栅极驱动器（10; 21p）和低侧栅极驱动器（10n; 21n），输出高电压电平的信号作为栅极 用于高端晶体管（Mp）和低端晶体管（Mn）的驱动信号（Gp，Gn）在所述的解决方案中，栅极驱动器（11）的高端和低端支路分别包括置位复位锁存器 ，24n），将所述信号输出（Qp，Qpn）作为栅极信号馈送到所述半桥或全桥驱动器（11）的相应晶体管（Mp，Mn）;差分电容电平移位器电路（23p，23n） 以低电压电平输入信号并输出​​高电压信号以驱动该组（S）和r 置位复位锁存器（24p，24n）的eset（R）输入。