公开(公告)号：WO2011079880A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005929

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/06 ,  H03K17/687 ,  B06B1/02 ,  H03K17/0812

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation switch (1) is described, inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting this high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) being inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (M1), inserted, in series to a first driving diode (D1), between the first voltage reference (Vss) and a first driving central circuit node (Xd) and a second driving transistor (M2), in turn inserted, in series with a second driving diode (D2), between the driving central circuit node (Xd) and the second supply voltage reference (-Vss) as well as a control transistor (MD) connected across a diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1), this control transistor (MD) having a control terminal connected to the driving central circuit node (Xd) through a low voltage decoupling block (6), in turn inserted between a first and a second substrate terminal (SS1, SS2) and also comprising a first and a second parasite capacitive element (Par1, Par2) connected to these first and second substrate terminals (SS1, SS2) as well as comprising at least one first decoupling transistor (M3) and one second decoupling transistor inserted (M4), being in parallel to each other and having control terminals connected to the first and second parasite capacitive elements (Par1, Par2), respectively.

Abstract translation: 描述了将低电压隔离开关（1）插入适于接收高电压信号（IM）的输入端（HVout）和适于将该高电压信号（IM）发送到负载的输出端（pzt）之间 PZ），其包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5），并且包括与第一驱动二极管串联插入的第一驱动晶体管（M1） D1），在第一电压基准（Vss）和第一驱动中心电路节点（Xd）和第二驱动晶体管（M2）之间，与第二驱动二极管（D2）串联插入驱动中心电路 节点（Xd）和第二电源电压参考（-Vss）以及连接在二极管块（7）之间的控制晶体管（MD），二极管块（7）包括至少一个第一和第二传输二极管（DN1，DN2），反相并联 即通过使第一二极管的阳极端子连接到阴极 在低电压隔离开关（1）的输入（HVout）和输出（pzt）端子之间，该控制晶体管（MD）具有连接到驱动中心电路节点的控制端（ Xd）通过低电压去耦块（6）进而插入在第一和第二衬底端子（SS1，SS2）之间，并且还包括连接到这些第一和第二衬底端子的第一和第二寄生电容元件（Par1，Par2） 衬底端子（SS1，SS2）以及包括彼此并联并具有连接到第一和第二寄生电容元件的控制端子的至少一个第一去耦晶体管（M3）和一个第二去耦晶体管（M4） Par1，Par2）。

公开(公告)号：WO2012085951A1

公开(公告)日：2012-06-28

申请号：PCT/IT2010/000511

申请日：2010-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation circuit (1) is described inserted between a connection node (HVout) to a matrix (2) of switches suitable for receiving a high voltage signal (IM) and a connection terminal (pzt) to a load (PZ) suitable for transmitting said high voltage signal (IM) to said load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, - Vss) and comprising at least a first driving transistor (M l), inserted, in series with a first driving diode (Dl), between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted, in series with a second diode (D2), between the driving central circuit node (Xc) and the second supply voltage reference (-Vss). The switch comprises an isolation block (8) connected to the connection terminal (pzt), to the connection node (HVout) and to the driving central circuit node (Xc) and comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the connection node (HVout) to the matrix (2) of switches and the connection terminal (pzt) to the load (PZ) of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc).

Abstract translation: 描述了一种低电压隔离电路（1），其插入到适于接收高电压信号（IM）的开关的矩阵（2）的连接节点（HVout）和适合于负载（PZ）的连接端子（pzt）之间 用于将所述高电压信号（IM）发送到包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5）的类型的所述负载（PZ），并且至少包括第一驱动晶体管 （M1）与第一驱动二极管（D1）串联插入在第一电压基准（Vss）和第一驱动中心电路节点（Xc）和第二驱动晶体管（M2）之间，然后插入 与驱动中心电路节点（Xc）和第二电源电压基准（-Vss）之间的第二二极管（D2）串联。 开关包括连接到连接端子（pzt）的隔离块（8），连接节点（HVout）和驱动中心电路节点（Xc），并且包括至少一个限压器块（6），二极管块 （7）和控制晶体管（MD），它们连接在连接节点（HVout）与开关矩阵（2）之间的二极管块（7）和连接端子（pzt）与负载（PZ）之间 低电压隔离开关（1）并具有连接到驱动中心电路节点（Xc）的控制端子（XD）。

公开(公告)号：WO2011079879A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005926

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/687 ,  H03K17/06 ,  B06B1/02 ,  H03K17/0812 ,  H03K17/0814

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/08142 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation circuit (1) is described inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting the high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (Ml), inserted between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted between the driving central circuit node (Xc) and the second supply voltage reference (-Vss) as well as an isolation block (8) connected to the connection terminal (pzt), to the input terminal (HVout) and, through a protection block (9) comprising a first and a second protection transistor (MD1, MD2), being in anti-series to each other and having control terminals receiving respective complementary protection driving signals (dr1, dr2), to the driving central circuit node (Xc), the isolation block (8) comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc) through the protection block (9), said diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having an anode terminal of said first diode connected to a cathode terminal of said second diode and vice versa.

Abstract translation: 描述了一种低压隔离电路（1），其插入适于接收高电压信号（IM）的输入端（HVout）和适于将高电压信号（IM）发送到负载（PZ）的输出端（pzt）之间 ）包括插入在第一和第二电压参考（Vss，-Vss）之间的至少一个驱动块（5），并且包括插入在第一电压参考（Vss）和第一电压参考（Vss）之间的第一驱动晶体管（M1） 驱动中心电路节点（Xc）和第二驱动晶体管（M2），其又插入在驱动中心电路节点（Xc）和第二电源电压参考（-Vss）之间，以及隔离块（8） 连接端子（pzt）到输入端子（HVout），并且通过包括第一和第二保护晶体管（MD1，MD2）的保护块（9）彼此反串联并且具有相应的控制端子 互补保护驾驶信号（dr1，dr 如图2所示，驱动中心电路节点（Xc），隔离块（8）包括至少一个限压器块（6），二极管块（7）和控制晶体管（MD） 在低压隔离开关（1）的输入（HVout）端子和输出端子（pzt）端子之间具有通过保护块（9）连接到驱动中心电路节点（Xc）的控制端子（XD）的块（7） ，所述二极管块（7）包括至少一个反并联连接的第一和第二传输二极管（DN1，DN2），即通过使所述第一二极管的阳极端子连接到所述第二二极管的阴极端子，反之亦然。

公开(公告)号：EP3217551A1

公开(公告)日：2017-09-13

申请号：EP16190816.5

申请日：2016-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  BOTTAREL, Valeria

IPC: H03K17/0412 ,  H03K3/3565 ,  H03K19/0185 ,  H03K17/06 ,  H03K17/687

Abstract: Gate driver circuit for a half bridge or full bridge output driver stage, identifying a high side branch connected to one or more high side transistors (Mp) and a low side branch connected to one or more low side transistors (Mn), comprising
a high side gate driver (10; 21p) and a low side gate driver (10n; 21n) receiving input signals at a low voltage level (VDD) and operating with a high voltage level (VPP), outputting signals at a high voltage level as gate driving signals (Gp, Gn) for the high side transistors (Mp) and low side transistors (Mn)
In the solution described the high side and the low side branches of the gate driver (11) include each
a set-reset latch (24p, 24n) which signal output (Qp, Qpn) is fed as gate signal to the corresponding transistor (Mp, Mn) of the half bridge or full bridge driver (11),
a differential capacitive level shifter circuit (23p, 23n) receiving said input signals at a low voltage level and outputting high voltage signals to drive the set (S) and reset (R) inputs of the set-reset latch (24p, 24n).

Abstract translation: 用于半桥或全桥输出驱动级的栅极驱动器电路，识别连接到一个或多个高侧晶体管（Mp）的高侧分支和连接到一个或多个低侧晶体管（Mn）的低侧分支，所述栅极驱动器电路包括高 接收低电压电平（VDD）的输入信号并以高电压电平（VPP）工作的高侧栅极驱动器（10; 21p）和低侧栅极驱动器（10n; 21n），输出高电压电平的信号作为栅极 用于高端晶体管（Mp）和低端晶体管（Mn）的驱动信号（Gp，Gn）在所述的解决方案中，栅极驱动器（11）的高端和低端支路分别包括置位复位锁存器 ，24n），将所述信号输出（Qp，Qpn）作为栅极信号馈送到所述半桥或全桥驱动器（11）的相应晶体管（Mp，Mn）;差分电容电平移位器电路（23p，23n） 以低电压电平输入信号并输出​​高电压信号以驱动该组（S）和r 置位复位锁存器（24p，24n）的eset（R）输入。

公开(公告)号：EP2656502A1

公开(公告)日：2013-10-30

申请号：EP10818066.2

申请日：2010-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

公开(公告)号：EP3217551B1

公开(公告)日：2020-07-29

申请号：EP16190816.5

申请日：2016-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  BOTTAREL, Valeria

IPC: H03K17/0412 ,  H03K3/3565 ,  H03K19/0185 ,  H03K17/06 ,  H03K17/687