公开(公告)号：EP1435623A1

公开(公告)日：2004-07-07

申请号：EP02425801.4

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Crippa, Luca ,  Ragone, Giancarlo

IPC: G11C16/10

CPC classification number: G11C16/12 ,  G11C11/5628

Abstract: The present invention relates to a method and an electronic device for stabilising the voltage on the drain terminals of multilevel non volatile memory cells (3) in the programming step. In the method the application of said voltage is provided through a drain voltage regulator (2) having an output (OUT) connected to said terminals in a common circuit node (A) by means of a metal line (4) conduction path having a parasitic intrinsic resistance (R pars ). Advantageously, a feedback path (5) is provided between the node (A) and an input of the regulator (2).

Abstract translation: 本发明涉及一种用于在电子稳定性伊辛上在编程步骤的多级非易失性存储器单元（3）的漏极端子处的电压的方法和设备。 在该方法中，所述电压的施加是通过在由金属线的方式共同的电路节点（A）连接到所述端子的漏极电压调节器（2），其具有在输出端（OUT）提供了具有寄生（4）导通路径 固有电阻（Rpars）。 有利地，所述节点（A）之间以及在调节器（2）的输入端提供的反馈路径（5）。

公开(公告)号：EP1750271A1

公开(公告)日：2007-02-07

申请号：EP05425558.3

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Sangalli, Miriam ,  Ragone, Giancarlo ,  Micheloni, Rino

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance (C LOAD ) of an integrated device at a certain charge-pump generated boosted voltage is safely implemented without obliging to integrate high voltage transistor structures of type of conductivity of the same sign of the boosted voltage (high-side transistors).
Another fulfilled objective is to provide a multilevel nonvolatile flash memory device comprising a boosted voltage regulator that can be entirely fabricated with a low cost nonvolatile flash memory fabrication process.
Basically, the multistage circuit for regulating the charge voltage or the discharge current of a capacitance in an integrated device, comprising at least a first stage and an output stage in cascade to the first stage and coupled to the capacitance, has the first stage supplied at an unboosted power supply voltage (V DD ) of the integrated device and the output stage supplied at an unregulated charge-pump generated boosted voltage (V PUMP ) and is composed of a transistor (M NOUT ) of type of conductivity opposite to the sign of the boosted voltage and of the power supply voltage.
The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up (R PULL-UP ) or a voltage limiter.

Abstract translation: 在一定的电荷泵产生的升压电压下，用于调节集成器件的电容（C LOAD）的充电电压或放电电流的多级电路被安全地实现，而不必集成将相同电导率的高电压晶体管结构 升压电压（高侧晶体管）的符号。 另一个实现的目标是提供一种多级非易失性闪存器件，其包括可以用低成本的非易失性闪速存储器制造工艺完全制造的升压型稳压器。 基本上，用于调节集成装置中的电容的充电电压或放电电流的多级电路包括至少第一级和级联到第一级并耦合到电容的输出级，第一级提供在 该集成装置的未升压的电源电压（V DD）和在未调节的电荷泵产生的升压电压（V PUMP）下提供的输出级，并且由一个导体类型的晶体管（M NOUT）构成， 升压电压和电源电压。 输出级晶体管的漏极通过电阻上拉（R PULL-UP）或限压器耦合到升压电压。

公开(公告)号：EP1727146A1

公开(公告)日：2006-11-29

申请号：EP05425348.9

申请日：2005-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Ragone, Giancarlo ,  Sangalli, Miriam ,  Crippa, Luca ,  Micheloni, Rino

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073 ,  H02M2001/007

Abstract: Voltage-boosting device having a supply input (9) receiving a supply voltage (Vdd), and a high-voltage output (3). The device (1) is formed by a plurality of charge-pump stages (14) series-connected between the supply input (9) and the high-voltage output (3). Each charge-pump stage (14) has a respective enabling input receiving an enabling signal (EN1, ..., ENn-1, ENn). A control circuit (4, 8) formed by a plurality of comparators (8.1, ..., 8.n-1, 8.n) is connected to the high-voltage output (3) and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output (3) and a plurality of reference voltages (REF1, ..., ..., REFn-1, REFn), one for each comparator. The charge-pump stages (14) are grouped into sets of stages (13.1, ..., 13.n-1, 13.n), and the stages belonging to a same set receive a same enabling signal (EN1, ENn-1, ENn); thus, as many comparators as there are sets of stages are present.

Abstract translation: 升压具有供电输入端（9），接收电源电压（Vdd）的装置，和一个高电压输出端（3）。 所述装置（1）通过的电荷泵级（14）串联连接在电源输入端（9）和所述输出高电压（3）之间形成的多个。 每个电荷泵级（14）具有一个respectivement使能输入处接收使能信号（EN1，...，ENN-1，ENN）。 控制电路（4,8）由比较器形成的多个（8.1，...，8.n.-1，8.n.）连接到高电压输出端（3）和基因率使能信号的基础上 在高电压输出端（3）的基准电压的多个电压之间的比较和（REF1，...，...，REF N-1，REF n）时，一个用于每个比较器。 电荷泵级（14）被分成组级（13.1，...，13.n-1，13.n），并且属于同一组的各个阶段接收相同的使能信号（EN1，ENn- 1，ENN）; 因此，许多比较，因为有套阶段都存在。

公开(公告)号：EP1677308A1

公开(公告)日：2006-07-05

申请号：EP05425001.4

申请日：2005-01-03

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: The output voltage ripple of a single stage or a multi-stage charge pump is significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor is always in a conduction state and is controlled with a voltage having a smaller ripple than the voltage output by the charge pump.

Abstract translation: 通过在电压发生器中引入共源共栅输出晶体管，可以显着降低单级或多级电荷泵的输出电压纹波。 在工作中，该输出晶体管总是处于导通状态，并且具有比电荷泵输出的电压小的纹波的电压来控制。

公开(公告)号：EP1724784B1

公开(公告)日：2008-07-23

申请号：EP05425347.1

申请日：2005-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Ragone, Giancarlo ,  Crippa, Luca ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

公开(公告)号：EP1892600A1

公开(公告)日：2008-02-27

申请号：EP06119456.9

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l.

Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G05F1/56

CPC classification number: G11C5/147 ,  G05F1/565 ,  G11C16/30

Abstract: A voltage regulator (150I) integrated in a chip of semiconductor material is proposed. The regulator has a first input terminal for receiving a first voltage (Vhv) and an output terminal for providing a regulated voltage (Vreg) being obtained from the first voltage, the regulator including: a differential amplifier (205I) for receiving a comparison voltage (Vref) and a feedback signal (Vfb) being a function of the regulated voltage, and for proving a regulation signal (Vr) according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor (MS) having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means (Rpup) between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage (Vdd) being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors (MS1-MS5) being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means (155) for controlling the auxiliary transistors according to the regulated voltage.

Abstract translation: 提出了集成在半导体材料芯片中的电压调节器（150I）。 调节器具有用于接收第一电压（Vhv）的第一输入端子和用于提供从第一电压获得的调节电压（Vreg）的输出端子，所述调节器包括：差分放大器（205I），用于接收比较电压 Vref）和作为调节电压的函数的反馈信号（Vfb），并且根据比较电压和反馈信号之间的比较来证明调节信号（Vr），所述差分放大器具有与 用于接收参考电压的参考端子和第二供电端子，具有用于接收调节信号的控制端子的调节晶体管（MS），以及通过第二端子和第二端子之间的负载装置（Rpup）耦合的导通第一端子和导通第二端子 参考端子和调节器的第一输入端子，调节晶体管的第二端子与输出端子耦合 ，其中所述差分放大器的第二电源端与所述调节器的第二输入端耦合，用于接收低于绝对值中的所述第一电压的第二电压（Vdd），并且其中所述调节器还包括一组 辅助晶体管（MS1-MS5）串联连接在调节晶体管的第二端子和调节器的输出端子之间，以及控制装置（155），用于根据调节电压控制辅助晶体管。

公开(公告)号：EP1435623B1

公开(公告)日：2008-06-04

申请号：EP02425801.4

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Crippa, Luca ,  Ragone, Giancarlo

IPC: G11C16/10

CPC classification number: G11C16/12 ,  G11C11/5628

公开(公告)号：EP1729302A1

公开(公告)日：2006-12-06

申请号：EP05104656.3

申请日：2005-05-31

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C7/04 ,  G11C16/30

Abstract: A circuit comprises at least one memory cell ( 110 ) adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator ( 300 ) is provided for generating a voltage (Vo) to be supplied to the at least one memory cell ( 110 ) for retrieving the data stored therein, the voltage generator including first means ( 305 ) adapted to cause the generated voltage take a value in a set of target values including at least one target value (Vr-1,Vr-2,Vr-3,Vfy-1,Vfy-2,Vfy-3), corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means ( Mt,Rs,325, R1,R2,330 ) for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element ( Mt ) having said electrical characteristic.

Abstract translation: 电路包括至少一个存储单元（110），其适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器（300），用于产生要提供给所述至少一个存储单元（110）的电压（Vo），用于检索存储在其中的数据，所述电压发生器包括第一装置（305），其适于使所产生的电压 在包含至少一个目标值（Vr-1，Vr-2，Vr-3，Vfy-1，Vfy-2，Vfy-3）的目标值集合中取值， 记忆单元 电压发生器包括用于使所产生的电压所采用的值根据规定的第二变化规律随温度变化的第二装置（Mt，Rs，325，R1，R2,330），该规定的第二变化规律利用具有所述电特性的补偿电路元件 。

公开(公告)号：EP1724784A1

公开(公告)日：2006-11-22

申请号：EP05425347.1

申请日：2005-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Ragone, Giancarlo ,  Crippa, Luca ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

Abstract translation: 的高电压开关（24）具有一个高电压输入端（29）接收高电压（HV），和输出端子（31）。 具有控制端子的导通晶体管（36），被连接在高电压输入端（29）和输出端子（31）之间。 电荷泵型的电压倍增电路（40）的输出被连接到控制终端。 电压倍增电路（40）是对称型，具有第一和第二电荷存储装置（41，42）接收周期性类型的时钟信号（CK），并具有第一电路支路（44，48 ）和第二电路支路（45，49），它们彼此对称和反相相对于所述时钟信号（CK）进行操作。