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    Improved delay locked loop circuit
    3.
    发明公开
    Improved delay locked loop circuit 有权
    VerbesserteVerzögerungsregelschleife

    公开(公告)号：EP1271786A1

    公开(公告)日：2003-01-02

    申请号：EP01830437.8

    申请日：2001-06-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano

    IPC: H03L7/081

    CPC classification number: H03L7/0814

    Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip - flop devices (37, ..., 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip - flop device (37, ..., 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27).

    Abstract translation: 本发明涉及一种用于产生锁定到输入信号（24）的相位的数字输出信号（56）的电路，包括多个延迟单元（42），包含第一值的第一寄存器（31），相位 检测器（26）和控制逻辑（25），其特征在于包括多个触发器装置（37，...，38），其中存储所述第一值，第二寄存器（30）包含第二值 多个加法器节点（33），适于将每个所述延迟单元（42）中的所述第二值与所述选择的触发器件（37，...，38）的内容相加，作为所述延迟单元（42） ）适于提供所述数字输出信号（56），所述相位检测器（26）接收所述输入信号（24）和所述数字输出信号（56），适于检测所述输入信号和所述数字输出信号 数字输出信号（56），所述控制逻辑（25）适于根据所述相位差（27）来控制所述第一和第二值。

    A converter for converting the level of differential signals
    4.
    发明公开
    A converter for converting the level of differential signals 审中-公开
    沃德勒zur Pegelwandlung von differentiellen信号

    公开(公告)号：EP1248371A1

    公开(公告)日：2002-10-09

    申请号：EP01830242.2

    申请日：2001-04-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Clerici, Gian Carlo ,  Tomasini, Luciano

    IPC: H03K19/0185 ,  H03F3/45

    CPC classification number: H03K19/018528 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45642 ,  H03F2203/45652 ,  H03F2203/45666 ,  H03F2203/45674 ,  H03F2203/45686

    Abstract: The converter comprises a differential amplifier (DIF) having two differential input signals of a first level (V in+ , V in- ) and two differential outputs (V out+ , V out- ), and two output buffers each comprising an inverter (I1, I2) with an input connected to an output of the differential amplifier. In order to produce a symmetrical circuit with output signals having leading and trailing edges and duty-cycles identical to those of the input signals, the converter comprises means (Rv) with adjustable conductivity through which the current (Io) of the differential amplifier passes, and a feedback circuit comprising a generator (Iref) which generates a reference potential (Vref) and is formed by circuit components of shapes and dimensions correlated in predetermined manner with the shapes and dimensions of the components of the inverter (I1, I2). The feedback circuit is connected between a node (N) of the differential amplifier (DIF) which, in operation, is at an intermediate potential between the potentials of the differential outputs, and a regulation terminal of the means (Rv) with adjustable conductivity, in order to regulate the supply voltage of the differential amplifier in a manner such as to keep the potential of the node (N) which is at the intermediate potential at the reference potential which is also the "trigger" potential of the inverters.

    Abstract translation: 差分电路（DIF）具有两个p沟道晶体管（M3'，M4'），其栅电极连接在节点（A，B）之间串联连接的两个相同电阻器（R）之间的连接节点（N） 而它们的源电极构成差分电路的电源端子。 反馈电路产生参考电位，并且在节点（N）和电阻器（Rv）之间连接比较器（CMP）以调节电源电压并将节点（N）维持在中间电位。

    Equaliser
    6.
    发明公开
    Equaliser 有权
    Entzerrer

    公开(公告)号：EP1154586A1

    公开(公告)日：2001-11-14

    申请号：EP00830343.0

    申请日：2000-05-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Milanese, Carlo Maria

    IPC: H04B3/14 ,  H03H11/04

    CPC classification number: H03H11/1291 ,  H03H11/0422 ,  H04B3/145

    Abstract: The present invention refers to a method and to an equalizer circuit of signals transmitted on a line. In an embodiment the equaliser circuit of signals transmitted on a line having an attenuation comprising: an analogical adaptive filter (1) applied in series to said line comprises at least two transconductance filters having a bias current (Pc1-Pcn) each and to which it is associated at least one pole and at least one zero the position in frequency of which in the working band (B) is variable in response to said bias current (Pc1-Pcn); a retroaction circuit (3, 4, 5, 6, 7) applied to the output of said filter (1) able to vary said bias current (Pc1-Pcn); said bias current (Pc1-Pcn) varies at the varying of said attenuation of said line; characterised in that said at least two transconductance filters have said bias current of prefixed value; said bias current is made to vary at the increasing of said attenuation so that said at least one pole is moved toward the high frequencies; said bias current is made to vary at the increasing of said attenuation so that said at least a zero is moved toward the low frequencies.

    Abstract translation: 本发明涉及在一条线路上发送的信号的方法和均衡器电路。 在一个实施例中，在具有衰减的线路上传输的信号的均衡器电路包括：与所述线串联施加的模拟自适应滤波器（1），包括至少两个具有偏置电流（Pc1-Pcn）的跨导滤波器， 至少一个极点和至少一个零点，工作频带（B）的频率位置响应于所述偏置电流（Pc1-Pcn）是可变的; 施加到能够改变所述偏置电流（Pc1-Pcn）的所述滤波器（1）的输出的回溯电路（3,4,5,6,7）; 所述偏置电流（Pc1-Pcn）在所述线路的衰减变化时变化; 其特征在于，所述至少两个跨导滤波器具有所述预定值的偏置电流; 所述偏置电流在所述衰减的增加中变化，使得所述至少一个极向高频移动; 所述偏置电流在所述衰减的增加中变化，使得所述至少一个零向低频移动。

    A telephone
    7.
    发明公开
    A telephone 有权
    Telephon

    公开(公告)号：EP1128654A1

    公开(公告)日：2001-08-29

    申请号：EP00830123.6

    申请日：2000-02-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Clerici, Giancarlo

    IPC: H04M19/08 ,  H04M1/74

    CPC classification number: H04M19/08 ,  H04M1/74

    Abstract: A telephone (100) comprises an acoustic alarm (125), conversation members (110), first control means (230a, 420) for the acoustic alarm, second control means (250a, 420) for the conversation members, first supply means (220, T1, Cl) and second supply means (240, T2, C, Ts, 405, 410) for absorbing energy from a telephone line (205), the first supply means (220, T1, C1) and the second supply means (240, T2, C, Ts, 405, 410) supplying the first control means (230a, 420) in a call condition and the second control means (250a, 420) in a conversation condition, respectively, wherein the first supply means (220, T1, C1) further supply the second control means (250a, 420) in the call condition.

    Abstract translation: 电话机（100）包括声音报警器（125），通话构件（110），用于声音报警器的第一控制装置（230a，420），用于对话构件的第二控制装置（250a，420），第一提供装置 ，T1，C1）和用于从电话线（205）吸收能量的第二供给装置（240，T2，C，Ts，405,410），第一供应装置（220，T1，C1）和第二供应装置 240，T2，C，Ts，405,410），分别在通话状态下提供第一控制装置（230a，420）和第二控制装置（250a，420），其中第一供应装置 ，T1，C1）进一步向所述呼叫状态提供所述第二控制装置（250a，420）。

    A circuit for compensating for the difference between the Vgs voltages of two MOS transistors
    8.
    发明公开
    A circuit for compensating for the difference between the Vgs voltages of two MOS transistors 有权
    Eine Schaltung zur Kompensation der Differenz der Vgs-Spannungen zweier MOS-Transistoren

    公开(公告)号：EP1094599A1

    公开(公告)日：2001-04-25

    申请号：EP99830662.5

    申请日：1999-10-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Guinea, Jesus

    IPC: H03F1/30 ,  H03F3/30

    CPC classification number: H03F1/301 ,  H03F3/3001

    Abstract: The difference between the Vgs voltages of a first MOS transistor (Mp) and a second MOS transistor (Mn) of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a circuit (10) comprising a third MOS transistor (Mp1) and a fourth MOS transistor (Mn1) which are of the same type as the first transistor (Mp) and the second transistor (Mn), respectively, and are formed in the same integrated circuit, means (VDD, Mp2, Mp3) for biasing the third transistor (Mp1) and the fourth transistor (Mn1), means (Mp4-Mp7) for measuring the difference between the Vgs voltages of the third transistor (Mp1) and the fourth transistor (Mn1), means (R1) for generating a compensation current (Io) which is a predetermined function of the difference measured, and means (Sp1-Sp3, Ro) for modifying the biasing of the first MOS transistor (Mp) and of the second MOS transistor (Mn) with the use of the compensation current (Io).

    Abstract translation: 由于制造过程的变化和/或其他参数的变化，集成电路的第一MOS晶体管（Mp）和第二MOS晶体管（Mn）的Vgs电压之间的差异由电路（10）补偿，包括 分别与第一晶体管（Mp）和第二晶体管（Mn）相同类型的第三MOS晶体管（Mp1）和第四MOS晶体管（Mn1），并形成在同一集成电路中， ，Mp2，Mp3），用于测量第三晶体管（Mp1）和第四晶体管（Mn1）的Vgs电压之间的差的装置（Mp4-Mp7），用于偏置第三晶体管（Mp1）和第四晶体管（Mn1） 用于产生作为测量差的预定函数的补偿电流（Io）的装置（R1），以及用于修改第一MOS晶体管（Mp）和第二MOS晶体管（Mp）的偏置的装置（Sp1-Sp3，Ro） Mn），使用补偿电流（Io）。

    A detector for detecting timing in a data flow
    9.
    发明公开
    A detector for detecting timing in a data flow 审中-公开
    Datenfluss ein Detektor zur Erfassung von Synchronisierung在einem Datenfluss

    公开(公告)号：EP1076435A1

    公开(公告)日：2001-02-14

    申请号：EP99830524.7

    申请日：1999-08-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano

    IPC: H04L7/033 ,  H03L7/081 ,  H03L7/07

    CPC classification number: H03L7/0814 ,  H03L7/07 ,  H04L7/0337

    Abstract: A detector for detecting timing in a digital data flow (BK) with a bit-time equal to T and with a coding which provides, at the beginning of the bit-time T, for no transition or for a transition of a first type or a transition of a second type and, in the middle of the bit-time T, for no transition or for a transition of the first type, comprises first circuit means (2) for generating four local timing signals (Q1-Q4) which have periods substantially equal to the bit-time and are out of phase with one another by 1/4 period, and second circuit means (3) for sampling the four local timing signals (Q1-Q4) upon each transition of the first type in the data flow and for determining, on the basis of the sampled states of the four local timing signals (Q1-Q4), whether a pair of reference signals (Q1-Q3) which are out of phase by one half period, of the four local timing signals (Q1-Q4), is advanced or delayed relative to the timing of the data flow, and consequently controlling the first circuit means in a manner such as to delay or to advance the four local timing signals (Q1-Q4).

    Abstract translation: 一种用于以比特时间等于T的数字数据流（BK）中的定时检测和用于在比特时间T开始时提供无转换或第一类型的转换的编码的检测器， 第二类型的转换，并且在位时间T的中间，用于无转换或第一类型的转换，包括用于产生四个本地定时信号（Q1-Q4）的第一电路装置（2），其具有 周期基本上等于比特时间，并且彼此相差1/4周期;以及第二电路装置（3），用于在第一类型的每个转换中对四个本地定时信号（Q1-Q4）进行采样 数据流，并且根据四个本地定时信号（Q1-Q4）的采样状态，确定四个本地定时信号（Q1-Q4）相差一个半周期的一对参考信号（Q1-Q3） 定时信号（Q1-Q4）相对于数据流的定时被提前或延迟，因此控制第一个循环 uit意味着以延迟或推进四个本地定时信号（Q1-Q4）的方式。

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