公开(公告)号：EP0978875A1

公开(公告)日：2000-02-09

申请号：EP98830489.5

申请日：1998-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Bacchetta, Maurizio ,  Vassalli, Omar ,  Zanotti, Luca

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit comprising lines of conductive material (4) for the electrical interconnection between parts of the circuit, and a layer of dielectric material (6), superimposed to the lines of conductive material (4). The lines of conductive material (4) have a vertical profile such that the smallest distance between two adjacent lines of conductive material is located at their upper surfaces.

Abstract translation: 一种半导体集成电路，包括导电材料（4），用于所述电路的部分之间的电互连的线，和电介质材料（6）构成的层，叠加到导电材料的线（4）。 导电材料（4）的线具有垂直轮廓搜索做导电材料构成的两个相邻线之间的最小距离位于它们的上表面。