公开(公告)号：EP1387394A3

公开(公告)日：2004-04-07

申请号：EP03077997.9

申请日：1997-04-15

Applicant: STMicroelectronics S.r.l.

Inventor： De Santi, Giorgio ,  Zanotti, Luca ,  Crisenza, Giuseppe

IPC: H01L23/31 ,  H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip, comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit (3, 3', 3"), characterized in that said layer of protective material (5) comprises a High-Density Plasma Chemical Vapor Deposition (HDPCVD) and by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface. (Figures 1 and 2).

Abstract translation: 包括至少一个集成电路芯片的集成电路器件的最终钝化过程，包括在所述至少一个集成电路（3,3'，3'）的顶表面上形成保护材料层（5）的步骤 “），其特征在于，所述保护材料层（5）包括高密度等离子体化学气相沉积（HDPCVD），并且通过提供所述保护材料层（5）的平面化的随后步骤，以获得具有 （图1和2）。

公开(公告)号：EP0978875A1

公开(公告)日：2000-02-09

申请号：EP98830489.5

申请日：1998-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Bacchetta, Maurizio ,  Vassalli, Omar ,  Zanotti, Luca

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit comprising lines of conductive material (4) for the electrical interconnection between parts of the circuit, and a layer of dielectric material (6), superimposed to the lines of conductive material (4). The lines of conductive material (4) have a vertical profile such that the smallest distance between two adjacent lines of conductive material is located at their upper surfaces.

Abstract translation: 一种半导体集成电路，包括导电材料（4），用于所述电路的部分之间的电互连的线，和电介质材料（6）构成的层，叠加到导电材料的线（4）。 导电材料（4）的线具有垂直轮廓搜索做导电材料构成的两个相邻线之间的最小距离位于它们的上表面。

公开(公告)号：EP0907202A1

公开(公告)日：1999-04-07

申请号：EP98105777.1

申请日：1998-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： DeSanti, Giorgio ,  Zanotti, Luca ,  Bacchetta, Maurizio Emanuele

IPC: H01L21/3105

CPC classification number: H01L21/31053

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), said devices comprising a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, into said trench regions (3), of a dielectric stack structure comprising a first layer (4) of oxide and a second layer (5) of oxide deposited over said first layer (4). Said first layer (4) is formed by high density plasma chemical vapor deposition (HDP-CVD) and said second layer (5) is a doped silicon oxide. A planarizing step is further applied by chemical-mechanical polishing (CMP) of said second layer (5).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面性的平面化方法，所述器件包括形成有栅极区域（2）的多个有源元件，所述栅极区域（2）以衬底（1）表面为傲，并且限定沟槽区域 ）。 该方法提供了在所述沟槽区域（3）中沉积包括氧化物的第一层（4）和沉积在所述第一层（4）上的氧化物的第二层（5））的介电堆叠结构。 所述第一层（4）通过高密度等离子体化学气相沉积（HDP-CVD）形成，所述第二层（5）是掺杂的氧化硅。 通过所述第二层（5）的化学机械抛光（CMP）进一步应用平坦化步骤。

公开(公告)号：EP2412665A1

公开(公告)日：2012-02-01

申请号：EP11175428.9

申请日：2011-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Ferrera, Marco ,  Perletti, Matteo ,  Varisco, Igor ,  Zanotti, Luca

IPC: B81C1/00 ,  B01L3/00 ,  G03F7/00 ,  B01D71/02

CPC classification number: B81C1/00119 ,  B01D67/0062 ,  B01D71/02 ,  B01D2325/021 ,  B01D2325/028 ,  B01L3/502707 ,  B01L3/502753 ,  B01L2300/0681 ,  B81B2201/10 ,  B81C1/00071 ,  B81C1/00087 ,  B81C2201/0133 ,  B81C2201/0157 ,  F04B19/006

Abstract: A process for manufacturing a micromechanical structure (25) envisages: forming a buried cavity (10) within a body (1, 12) of semiconductor material, separated from a top surface (12a) of the body by a first surface layer (12); and forming an access duct (18a) for fluid communication between the buried cavity (10) and an external environment. The method envisages: forming an etching mask (14) on the top surface (12a) at a first access area (17a); forming a second surface layer (15) on the top surface (12a) and on the etching mask (14); carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer (15), and an underlying portion of the first surface layer (12) not covered by the etching mask (14) until the buried cavity is reached, thus forming both the first access duct (18a) and a filter element (20), set between the first access duct and the same buried cavity.

Abstract translation: 一种用于制造微机械结构（25）设想过程：半导体材料的主体（1，12）内形成掩埋空腔（10），由第一表面层与所述主体的顶面（12a）的分离（12） ; 以及形成到埋入腔（10）之间，并与外部环境中访问管道（18）流体连通。 该方法设想：在在第一接入区域（17a）的蚀刻顶表面（12A）上掩模（14）成形; 形成所述顶面（12A）上的第二表面层（15）和在蚀刻掩模（14）; 进行蚀刻：如以除去，在对应于所述第一接入区，第二表面层（15）的一部分的位置，并在第一表面层（12）未包括的蚀刻掩模的下层部分（14 ）达到掩埋空腔直到，从而形成两个第一接入管道（18a）和一个过滤器元件（20），所述第一进出管道和相同的掩埋空腔之间。

公开(公告)号：EP1659640A1

公开(公告)日：2006-05-24

申请号：EP04425867.1

申请日：2004-11-19

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Riboli, Paolo ,  Zanotti, Luca ,  Palmieri, Michele ,  Mottura, Marta

IPC: H01L31/18 ,  H01L31/068 ,  H01L21/762

CPC classification number: H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of fabricating a wafer-size photovoltaic cell module capable of drastically reducing the overall costs of photovoltaic cells of enhanced efficiency realized on a monocrystalline silicon substrate comprises the steps of:

defining an integrated cellular structure, of a light converting monolateral or bilateral junction diode in the epitaxially grown detachable layer, including a first deposited metal current collecting terminal of the diode;
laminating onto the surface the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions;
immersing the wafer in a hydrofluoric acid solution causing detachment of the processed epitaxially grown silicon layer laminated with the film of optical grade plastic material;
polishing the surface of separation of the detached processed epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a relatively low temperature tolerable by the film of optical grade plastic material.

Abstract translation: 制造能够大幅度地减少的实现上的单晶硅衬底增强效率的光伏电池的总成本的晶片尺寸太阳能电池组件的方法，包括以下步骤：光的集成蜂窝结构的 - 定义，转换单边或双边结二极管 在外延生长层可拆卸的，包括第一熔敷金属集流二极管的端子; 到表面上的处理外延生长可分离层层压的光学级塑料材料，以氢氟酸溶液腐蚀的膜; 浸渍在曹景伟层叠有光学级塑料材料制成的膜经处理的外延生长的硅层的剥离氢氟酸溶液的晶片; 抛光处理分离外延生长层的分离表面以及形成第二金属电流在相对低的温度下的光学级塑料材料制成的膜可容忍收集二极管通过金属的掩蔽沉积的终端。

公开(公告)号：EP1387394A2

公开(公告)日：2004-02-04

申请号：EP03077997.9

申请日：1997-04-15

Applicant: STMicroelectronics S.r.l.

Inventor： De Santi, Giorgio ,  Zanotti, Luca ,  Crisenza, Giuseppe

IPC: H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip, comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit (3, 3', 3"), characterized in that said layer of protective material (5) comprises a High-Density Plasma Chemical Vapor Deposition (HDPCVD) and by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface. (Figures 1 and 2).

Abstract translation: 一种包括至少一个集成电路芯片的集成电路器件的最终钝化过程，包括在至少一个集成电路（3,3'，3）的顶表面上形成保护材料层（5）的步骤， “），其特征在于，所述保护材料层（5）包括高密度等离子体化学气相沉积（HDPCVD）并且通过提供所述保护材料层（5）的平坦化的后续步骤以获得具有 基本平坦的顶面（图1和2）。

公开(公告)号：EP0907201A1

公开(公告)日：1999-04-07

申请号：EP97830491.3

申请日：1997-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： DeSanti, Giorgio ,  Zanotti, Luca ,  Bacchetta, Maurizio Emanuele

IPC: H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/31051

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), said devices comprising a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, into said trench regions (3), of a dielectric ply structure comprising a first layer (4) of oxide and a second layer (5) of oxide deposited over said first layer (4). Said first layer (4) is formed by high density plasma chemical vapor deposition (HDP-CVD) and said second layer (5) is a doped silicon oxide. A planarizing step is further applied by chemio-mechanical polishing (CMP) of said second layer (5).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面性的平面化方法，所述器件包括由栅极区（2）形成的多个有源元件，栅极区（2）以衬底（1）表面为突出且限定沟槽区（3 ）之间。 该方法提供了在所述沟槽区域（3）中沉积电介质片层结构，该电介质片层结构包括氧化物的第一层（4）和沉积在所述第一层（4）上的第二氧化物层（5）。 所述第一层（4）由高密度等离子体化学气相沉积（HDP-CVD）形成，所述第二层（5）为掺杂氧化硅。 通过所述第二层（5）的化学机械抛光（CMP）进一步施加平面化步骤。

公开(公告)号：EP0887847A1

公开(公告)日：1998-12-30

申请号：EP97830173.7

申请日：1997-04-15

Applicant: STMicroelectronics S.r.l.

Inventor： De Santi, Giorgio ,  Crisenza, Giuseppe ,  Zanotti, Luca

IPC: H01L21/3105 ,  H01L21/98

CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip (3;3',3''), comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit, characterized by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface.

Abstract translation: 包括至少一个集成电路芯片（3; 3'，3“）的集成电路器件的最终钝化过程，包括在所述至少一个顶表面上形成保护材料层（5）的步骤 一个集成电路，其特征在于提供所述保护材料层（5）的平面化的随后步骤，以获得具有基本平坦的顶表面的保护层。

公开(公告)号：EP1521300A1

公开(公告)日：2005-04-06

申请号：EP03425642.0

申请日：2003-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zanotti, Luca

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit structure (1) integrated on a semiconductor substrate (2) comprising a plurality of electronic devices (3) covered by a first insulating layer (4), wherein said first dielectric layer (4) is covered by a closing layer (5) whereon a plurality of conductive interconnection levels are realised, being electrically connected to each other and separated from each other by means of a single insulating layer (13).

Abstract translation: 一种电路结构集成（2），包括由第一绝缘层（4）覆盖的电子设备（3）的多个A半导体衬底（1）上，worin所述第一介电层（4）由一个封闭层覆盖（5） 其上的导电互连层的多元性被实现，被电由单个绝缘层（13）被连接到海誓山盟和从海誓山盟分离。

公开(公告)号：EP0720223B1

公开(公告)日：2003-03-26

申请号：EP94830591.7

申请日：1994-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Bacchetta, Maurizio ,  Zanotti, Luca ,  Queirolo, Giuseppe

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/532

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24942 ,  Y10T428/265 ,  Y10T428/30 ,  H01L2924/00