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">1.发明公开Integrated circuit comprising conductive lines with "negative" profile and related method of fabrication 审中-公开组成的导电线与“负”轮廓和制造方法的集成电路
公开(公告)号：EP0978875A1
公开(公告)日：2000-02-09
申请号：EP98830489.5
申请日：1998-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Bacchetta, Maurizio , Vassalli, Omar , Zanotti, Luca
IPC: H01L23/522 , H01L23/528
CPC classification number: H01L23/5222 , H01L23/5283 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor integrated circuit comprising lines of conductive material (4) for the electrical interconnection between parts of the circuit, and a layer of dielectric material (6), superimposed to the lines of conductive material (4). The lines of conductive material (4) have a vertical profile such that the smallest distance between two adjacent lines of conductive material is located at their upper surfaces.
Abstract translation: 一种半导体集成电路，包括导电材料（4），用于所述电路的部分之间的电互连的线，和电介质材料（6）构成的层，叠加到导电材料的线（4）。 导电材料（4）的线具有垂直轮廓搜索做导电材料构成的两个相邻线之间的最小距离位于它们的上表面。
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2.发明授权Process for the production of a semiconductor device having better interface adhesion between dielectric layers 失效半导体装置的制造方法具有改进的介电层之间的粘附性
公开(公告)号：EP0720223B1
公开(公告)日：2003-03-26
申请号：EP94830591.7
申请日：1994-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Bacchetta, Maurizio , Zanotti, Luca , Queirolo, Giuseppe
IPC: H01L23/31 , H01L23/29 , H01L23/532
CPC classification number: H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/31608 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , Y10T428/24942 , Y10T428/265 , Y10T428/30 , H01L2924/00
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3.发明授权Planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices 失效Planariezierungsverfahren用于生产集成电路，特别是用于非液体半导体存储器件的
公开(公告)号：EP0677869B1
公开(公告)日：1999-03-17
申请号：EP94830167.6
申请日：1994-04-12
Applicant: STMicroelectronics S.r.l.
Inventor： Losavio, Aldo , Bacchetta, Maurizio
IPC: H01L21/3105 , H01L21/768
CPC classification number: H01L21/76819 , H01L21/31051 , H01L2924/0002 , H01L2924/00
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